Instruction Set Design: Part 2 MIPS

1
Instruction Set Design Part 2 - MIPS

• Shivkumar Kalyanaraman
• Rensselaer Polytechnic Institute
• shivkuma_at_ecse.rpi.edu
• http//www.ecse.rpi.edu/Homepages/shivkuma

2
Overview

• Introduction to subset of MIPS instruction set
• Examples of assembly language programming showing
  realizations of higher level language concepts
  like procedures, arithmetic, decisions etc

3
Operations

• add a, b, c
• Compiled version of a b c
• Always exactly three operands DP1 Simplicity
  favors regularity
• The first operand (a) will hold result

4
Operands

• Arithmetic operands must be registers !
• MIPS registers 32 bits long 1 word
• MIPS has 32 registers only DP2 Smaller is
  Faster
• As far as possible variables reside in registers
• Registers s0 - s7 variables, t0-t7
  (temporaries) etc
• Exercise What is the compiled version of
• f (gh) - (ij). Assume f,g,h,i,j are in
  registers s0-s4 respectively.

5
Memory and Data Transfer

• Registers too small for arrays gt stored in
  memory
• Memory looks like a large single dimensional
  array of 230 words
• Require data transfer instructions to move data
  between memory and registers.
• Load word lw, Store word sw
• Example Compile g h A8
• Assume that A is an array of words and the base
  address of A is in s3 and g,h in s1 and s2

6
Alignment restriction

• MIPS memory is byte-addressable
• MIPS word addresses differ by 4.
• Restriction Words must start at addresses that
  are multiples of 4
• Big endian addressing Word address refers to
  leftmost or big end byte
• Affects array index To get 8th word from base
  register s3, we should add an offset of 84
  32!
• Eg A12 h A8. Assume h in s2, and base
  is in s3.

7
Instruction Format

• Machine representation for
• add t0, s1, s2

0
17
18
8
0
32
op
rs
rt
rd
shamt
funct
6 bits
5 bits
6 bits
5 bits
5 bits
5 bits

• Op operation code funct variant of operation
• rs, rt first and second source operands
• rd destination operand
• shamt shift amount (unused here)

8
Instruction Format (contd)

• Problem what if we wanted longer operands (eg
  constant in lw) ?
• DP3 Good design demands good compromises
• Keep all instructions same length
• Have different formats for different instruction
  types. Eg R-type (prev slide) and I-type (below)
• Keep formats similar (common field positions)

op
rs
rt
address
6 bits
5 bits
16 bits
5 bits
9
Decisions

• Higher level constructs
• if-then-else, switch-case, goto, while-do,
  do-while, for-loops etc
• MIPS instructions to emulate if goto
• beq register1, register2, L1 Branch if equal
• bne register1, register2, L1 Branch if not
  equal
• Eg if (ij) go to L1
• f g h // Assume f thru j in
  s0 thru s4
• L1 f f - i

10
Decisions if-then-else, loops

• Unconditional branch for if-then-else and loops
• j Exit Jump to Exit
• Example if (ij) f gh else f g - h
• Compiler note test for opposite condition more
  efficient

11
Decisions Miscellaneous

• For ltor gt tests use slt (set on less than)
  in combination with beq and bne. Use zero as a
  register which always contains zero. Eg if (s1
  lt s2)
• slt t0, s0, s1
• bne t0, zero, L1
• Case/Switch efficient if alternative instruction
  sequences specified through an address table.
• MIPS provides jump register (jr) instruction to
  index through such a table

12
Instruction formats
op rs rt rd shamt funct
R I J
op rs rt 16 bit address
op 26 bit address

• DP3 Good design demands good compromises
• Addresses in the J-format are not 32 bits
• How do we handle this with jump ?
• gt Jump instructions just use high order bits of
  PC.
• gt Program must not cross address boundaries of
  256 MB

13
To summarize so far ...
14
Procedures

• Steps
• Place parameters in known place, Transfer control
• Acquire storage resources, Perform task
• Place result in known place, Return control
• Register allocation
• a0-a3 argument registers
• v0-v1 to return values
• ra return address register
• jal ProcAddress jump and link
• Jumps to ProcAddress
• Simultaneously saves address of the following
  instruction (ProgramCounter 4) in register ra

15
Procedure call/return
jal X
PC
raPC4
PC 4
X
jr ra
16
Procedures (contd)

• Need more arguments or values or local variables
  ?
• Create space in a stack for local variables
• Save registers to be preserved onto a stack
• Pointer to top of stack sp
• Stack grows downward (high to low addresses)
• Push gt subtract from sp Pop gt add to sp

17
Procedures (contd)

• Eg int example (int g, int h, int i, int j)
• int f
• f (gh) - (ij)
• return f

18
Procedures (contd)

• Conventions
• What is preserved s0-s7, sp, ra, stack above
  stack pointer
• What is not preserved t0-t9, a0-a3, v0-v1,
  stack below stack pointer
• Nested procedures Eg recursion
• Caller pushes any argument (ai) and temporary
  registers (ti) it wants preserved
• Callee pushes saved regs (si) and return address
  reg (ra)
• Activation record Portion of stack containing
  procedures saved registers and local variables.
  Also called stack frame.
• fp frame pointer points to first word in stack
  frame. Does not change as stack grows/shrinks.

19
Register conventions
20
Bytes, Half words, Words

• MIPS allows characters (one byte), short integers
  (two bytes) and words (4 bytes)
• Operations lb, sb (load/store byte)

21
Constants Immediate Addressing

• Small constants are used quite frequently (50 of
  operands) e.g., A A 5 B B 1 C
  C - 18
• Solution Have constants in the I-type
  instructions itself !
• MIPS Instructions addi 29, 29, 4 slti 8,
  18, 10 andi 29, 29, 6 ori 29, 29, 4

22
Larger constants

• We'd like to be able to load a 32 bit constant
  into a register
• Must use two instructions, new "load upper
  immediate" instructionlui t0, 1010101010101010
• Next get the lower order bits right, i.e., ori
  t0, t0, 1010101010101010
• This is usually done by the assembler using the
  register at
• DP4 Make the common case fast !

1010101010101010
0000000000000000
0000000000000000
1010101010101010
ori
23
Arithmetic Register addressing

• Operands in registers
• Allows 3 operands per operation

24
Addresses in branches and jumps

• Instructions
• bne t4,t5,Label Next instruction is at Label
  if t4 ! t5
• beq t4,t5,Label Next instruction is at Label
  if t4 t5
• j Label Next instruction is at Label
• Formats
• Addresses are not 32 bits !

op rs rt 16 bit address
I J
op 26 bit address
25
Addressing in branches and jumps

• Base addressing and PC-relative addressing
• Add 16-bit label to base register (or PC)

• Pseudo-direct addressing restrict programs to
  lie within 256 MB boundaries
• and use 26 bits to directly address the
  instruction

5
.

P
s
e
u
d
o
d
i
r
e
c
t

a
d
d
r
e
s
s
i
n
g
M
e
m
o
r
y
o
p
A
d
d
r
e
s
s
W
o
r
d
P
C
26
MIPS addressing modes summary
1
.

I
m
m
e
d
i
a
t
e

a
d
d
r
e
s
s
i
n
g
o
p
r
s
r
t
I
m
m
e
d
i
a
t
e
2
.

R
e
g
i
s
t
e
r

a
d
d
r
e
s
s
i
n
g
o
p
r
s
r
t
r
d
.

.

.
f
u
n
c
t
R
e
g
i
s
t
e
r
s
R
e
g
i
s
t
e
r
3
.

B
a
s
e

a
d
d
r
e
s
s
i
n
g
M
e
m
o
r
y
o
p
r
s
r
t
A
d
d
r
e
s
s

B
y
t
e
H
a
l
f
w
o
r
d
W
o
r
d
R
e
g
i
s
t
e
r
4
.

P
C
-
r
e
l
a
t
i
v
e

a
d
d
r
e
s
s
i
n
g
M
e
m
o
r
y
o
p
r
s
r
t
A
d
d
r
e
s
s

W
o
r
d
P
C
5
.

P
s
e
u
d
o
d
i
r
e
c
t

a
d
d
r
e
s
s
i
n
g
M
e
m
o
r
y
o
p
A
d
d
r
e
s
s
W
o
r
d
P
C
27
Summary

• MIPS instruction formats and conventions
• Arithmetic, load/store, decision statements
• Procedure implementation model in MIPS
• Addressing modes in MIPS
• Assembly language programming examples
• Suggested reading Sec 3.10 which is a full
  example