More Combinational Circuits and Sequential Circuits

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• More Combinational Circuits and Sequential
  Circuits

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Decoder
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Designing a Decoder
4 outputs gt 4 functions of 2 inputs
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Inside the 2-to-4 Decoder
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Inside the 2-to-4 Decoder w/ ENB
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Encoder
Input a bit pattern with many 0s and one and
only one 1. Output the binary encoding of the
number of the input that is active (1).
This is a 8-to-3 encoder.
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ExerciseDesigning an Encoder
2 outputs gt 2 functions of 4 inputs
Show the internal circuit for this component w/
an ENB input.
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The 1-bit Logic Unit
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The 1-bit Full-Adder
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The 1-bit ALU
Operations performed
Claim This ALU works with 2s complement integer
representation.
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A 32-bit ALU
Question Can this ALU detect overflow in
addition or in subtraction?
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Almost a 32-bit MIPSALU
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The MIPS ALU
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Memory Elements

• Nothing weve seen so far has the ability to
  store data, not even a single bit.
• When you remove (or change) any input, after a
  propagation delay, the output correspondingly
  changes.
• As we well know, a computer must remember
  information in order to carry out computations.

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The S-R Latch
0
0
0
0
1
0
1
1
1
1
Note state changes happen when they happen. You
cant control when.
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The D Flip-Flop
When the clock line transitions from 0 to 1, the
value presented at the D line is read into the
component and becomes the state of the flip-flop.
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Clocks
A clock signal is a square waveform (usually
symmetrical) defined by a period or cycle time.
It is a reference signal that allows one to
measure the passage of time. The clock rate or
clock frequency is the inverse of the cycle time
and is measured in Hertz
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Clock Edges
Our circuits will all be edge-triggered, that is,
things happen only when clock values change for
0-to-1 or 1-to-0. Note that the clock period must
be chosen so that it is long enough for all
signals in a combinational circuit to stabilize.
Definition setup time is the minimum time that
the inputs must be valid (or stable) before the
clock edge .
Definition hold time is the minimum time during
which the inputs must stay valid after the clock
edge .
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Register More than a Single Bit

clock
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Register File More than a Single Register
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Inside a Register File Read Ports
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Inside a Register File Write Ports
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More and More Bits
Flip-flop one single bit
Register a set of bits
Register file a set of registers
Whats next?
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Memory
n
Memory Chip Width word size m bits Height
2n words Bit size Height x Width
Address
m
m
Write enable
Output enable
Chip select
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Sequential LogicFinite State Machines
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Sequential Logic
Fact Combinational logic has no memory.
Question What would a circuit with memory be
able to do that a combinational circuit cannot do?
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The Structure of a Finite State Machine
Finite state machine A sequential logic function
consisting of a set of inputs and outputs, a
next-state function that maps the current state
and the inputs to a new state, and an output
function that maps the current state and possibly
the inputs to a set of asserted outputs. Next-sta
te function A combinational function that, given
the inputs and the current state, determines the
next state of a finite state machine.
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Example A Counter
C/010
D/011
B/001
E/100
A/000
No need for inputs other than a reference signal
for timekeeping.
F/101
H/111
G/110
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Example A Counter
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Circuit for the Counter
Combinational logic generates next state
(next-state function)
Memory stores current state
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Question What does this circuit do?