Simulation and Synthesis of Quantum Circuits

1
Simulation and Synthesisof Quantum Circuits

• Igor L. Markov and John P. Hayes
• Advanced Computer Architecture Laboratory
• University of Michigan, EECS

2
Quantum Circuits Group _at_UMich

• PIs Prof. Igor Markov Prof. John Hayes
• Postdoc Dr. Ketan Patel (circuit testing)
• Graduate Student Researchers Fellows
• George Viamontes (simulation/QuIDDs)
• Manoj Rajagopalan (simulation, synthesis by SA)
• DoRon Motter (circuit complexity)
• Smita Krishnaswamy (quantum clocks)
• Parmoon Seddighrad (technology-specific opt.)

3
High-level Assumptions and Goals

• Assumption physicists will have promising
  technology prototypes
• Expectation at 20 qubits, design complexity
  becomes a serious issue
• Even at 20 bits, optimal logic synthesis is
  difficult
• Our job improve the competitiveness of
  prototypes and facilitate applications
• Address specific design objectives and trade-offs
• Discover scalable design/simulation techniques
• Connect design techniques with applications
• Id new types of q. circuits and new applications

4
Our Expertise

• Computer Architecture
• Electronic Design Automation / VLSI CAD
• Automated Synthesis of Logic Circuits
• Formal Verification
• Circuit Layout
• Circuit Testing
• Design analysis of algorithms/heuristics
• Including Algorithm Engineering(implementation,
  evaluation, integration)

5
Design Productivity Gap

• NTRS / ITRS Design Productivity Gapis roughly
  49 a year vs 21 a year
• Is quantum D. P. G. looming ?

6
Fundamental Optimizations

• Research in Design Automationtargets core
  computational obstacles
• E.g., scalability in terms of runtime QOR
• Value in trying to solve wrong problems
• Many optimization algorithmscan be easily
  re-focused
• Different objectives and constraints
• Example Simulated Annealing

7
Research Themes (1)

• From classical to quantum
• Use classical reversible circuits as simple
  test-bed
• Leverage and generalize known design
  techniquesfor classical circuits
• Simulation-driven design
• Support for quantum circuit testing
• Ability to incrementally improve designsbased on
  results of simulations/tests
• Ability to empirically evaluate quantum
  designsand algorithms without easily-provable
  properties

8
Research Themes (2)

• New types of quantum circuits
• Case-by-case automatic synthesis versus
  asymptotic constructions
• Real life vs theory (cf. synthesis of classical
  random logic)
• Empirical performance versus provable results
• Separate design and simulation/test stages
• Example sequential versus combinational
• New applications
• Enabled by automatic synthesis
• Leveraging new types of circuits, e.g., sequential

9
Research Topics (1)

• Synthesis algorithms for classical logic as
  subroutines for quantum circuit synthesis
• Algebraic approaches to circuit synthesis
• E.g., abstract and computational group theory
• Matrix factorizations QR, ILU, CS and KAK
• Special-case synthesis, e.g., Grover oracles
• Generic quantum circuit synthesis and reduction
• Dynamic programming
• Annealing and other heuristics

10
Research Topics (2)

• Automatic error correction during synthesis
• Efficient simulation of quantum circuits
• Graph-theoretical algorithms based on common
  arithmetic sub-expressions (QUIDDs)
• New types of quantum circuits
• Quantum clocks and other sequential circuits
• New and old applications
• Quantum optimization algorithms (heuristics)
• Memory-savvy versions of known algorithms

11
Remaining Part Of The Talk

• Synthesis of Reversible Logic Circuitsand
  Applications to Grovers Search
• Synthesis of Quantum Circuitsby Simulated
  Annealing
• High-performance Simulationof Quantum Circuits
  using QuIDDs

12
Optimal Synthesis ofReversible Logic Circuits

• Vivek V. Shende, Aditya K. Prasad, Igor L.
  Markov and John P. Hayes
• Advanced Computer Architecture Laboratory
• University of Michigan, EECS

13
Outline

• Motivation
• Real-world Applications
• Asymptotically Zero-Energy circuits
• Links to Quantum Computation
• Background
• Theoretical Results
• Synthesis of Optimal Circuits
• An Application to Quantum Computing

14
Real-world Applications

• Many inherently reversible applications
• Info. is re-coded, but none is lost or added
• Digital signal processing
• Cryptography
• Communications
• Computer graphics
• Network congestion modeling

15
Links to Quantum Computation

• Quantum operations are all reversible
• Every (classical) reversible circuit may be
  implemented in quantum technology, with overhead
• Pseudo-classical subroutines of quantum algos
• Can be implemented in classical reversible logic
  circuits
• Groverssearch

16
Outline

• Motivation
• Background
• Reversibility
• Permutations
• Known Facts
• Theoretical Results
• Synthesis of Optimal Circuits
• An Application to Quantum Computing

17
Reversibility in Logic Gates

• Definition reversible logic gate
• input wires output wires
• Permutes the set of input values
• Examples
• Inverter
• 2-input, 2-output SWAP (S) gate
• k-CNOT gate
• (k1)-inputs and (k1)-outputs
• Values on the first k wires are unchanged
• The last value is flipped if the first k were all
  1

18
Reversibility in Logic Circuits

• DefinitionA combinational logic circuit is
  reversible iff
• It contains only reversible gates
• It has no fan-out
• It is acyclic as a directed multi-graph
• TheoremA reversible circuit must
• Have as many input wires as output wires
• Permute the set of input values

19
A Reversible Circuit and Truth Table
x y z x y z
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 1 1 1
1 1 1 1 1 0
Equivalent to a single CNOT gate
20
Circuit Equivalences

• Circuit equivalences useful in synthesis
• More will be shown later

21
Reversible Circuits Permutations

• A reversible gate (or circuit) with n inputs and
  n outputs has
• 2n possible input values
• 2n possible output values
• The function it computes on this set must, by
  definition, be a permutation
• The set of such permutations is called S2n

22
Basic Facts About Permutations

• Permutations are multiplied by first applying
  one, then the other
• example (1,2)?(2,3) (1,3,2)
• A transposition
• permutes exactly two elements
• does not change any others
• Every permutation can be writtenas a product of
  transpositions

23
Even Permutations

• Consider all possible decompositionsof a
  permutation into transpositions
• Theorem The parity of the numberof
  transpositions is constant
• Definition Even permutations are those for which
  the number of transpositions is even

24
Known Facts

• Fact 1 Consider a reversible circuit
• n1 inputs and n1 outputs
• Built from gates which have at most n inputs
  and n outputs
• Must compute an even permutation
• Fact 2 A universal gate library
• CNOT, NOT, and TOFFOLI (CNT)
• Temporary storage may be required

25
Temporary Storage
26
Outline

• Motivation
• Background
• Theoretical Results
• Zero-storage Circuits
• Reversible De Morgans Laws
• Synthesis of Optimal Circuits
• An Application to Quantum Computing

27
Minimizing Temporary Storage

• Consider CNT circuits
• Theorem even permutations computableby circuits
  without temporary storage
• Theorem odd permutations computablewith one
  line of temporary storage
• Same holds for NT and CNTS circuits
• The proof is constructive and may be used as a
  synthesis heuristic

28
Outline of Proof

• Explicitly construct a circuit to computean
  arbitrary pair of disjoint transpositions (A,
  B) (C, D) is okay (A, B) (B, C) is not
• Pick an even permutation
• Decompose it into transpositions
• Will have an even number of transpositions
• Pair these up, guaranteeing disjointness
• Apply construction to each pair

29
Flowchart of Proof
30
Reversible De Morgans Laws (1)

• De Morgans Laws
• Can send inverters to inputs in AND/OR/NOT
  circuits
• Reversible De Morgans Laws
• Can send inverters to inputs in CNT circuits
• Rules exist to move TOFFOLI and CNOT gates
• However, it is not always possibleto push all
  CNOT gates to the inputs
• Oddly enough, all CNOT gates can be pushed to the
  middle of the circuit

31
Reversible De Morgans Laws (2)
32
Reversible De Morgans Laws (3)
33
Outline

• Motivation
• Background
• Theoretical Results
• Synthesis of Optimal Circuits
• Optimality
• DFID Search Algorithm
• Circuit Libraries
• An Application to Quantum Computing

34
Optimality

• The cost of a circuit is its gate count
• Other cost functions can be considered
• Definition optimal reversible circuit
• no circuit with fewer gates computes the same
  permutation
• Theorem a sub-circuit of an optimal circuit is
  optimal
• Proof otherwise, can improve the sub-circuit

35
The Search Procedure

• Depth First Iterative Deepening Search
• Checks all possible circuits of cost 1, then all
  possible circuits of cost 2, etc
• Avoids the memory blowup of BFS
• Still finds optimal solutions (unlike DFS)
• Checking circuits of cost less than n is much
  faster than processing cost-n circuits

36
Dynamic Prog Circuit Libraries

• DFID search requires a subroutine to checkall
  circuits of cost n, for arbitrary n
• Called iteratively for 1n
• Only need to check locally optimal circuits
• Build optimal circuit library bottom up by DP
• Index optimal circuits by computed permutation
• In practice use hash_map datastruct from STL

37
Synthesis Algorithm
38
Empirical Circuit Synthesis

• Consider all reversible functions on 3 wires(8!
  40,320 functions)
• For each gate library fromN, C, T, NC, CT, NT,
  CNT, CNTS
• Is it universal?
• How many functions can it synthesize?
• How long does it take to synthesize circuits?
• What are largest optimal circuits?

39
Optimal Circuit Sizes
Size N C T NC CT NT CNT CNTS
12 0 0 0 0 0 47 0 0
11 0 0 0 0 0 1690 0 0
10 0 0 0 0 0 8363 0 0
9 0 0 0 0 0 12237 0 0
8 0 0 0 0 6 9339 577 32
7 0 0 0 14 386 5097 10253 6817
6 0 2 0 215 1688 2262 17049 17531
5 0 24 0 474 1784 870 8921 11194
4 0 60 5 393 845 296 2780 3752
3 1 51 9 187 261 88 625 844
2 3 24 6 51 60 24 102 135
1 3 6 3 9 9 6 12 15
0 1 1 1 1 1 1 1 1
Total 8 168 24 1344 5040 40320 40320 40320
Time, s 1 1 1 30 215 97 40 15
40
Largest Optimal Circuits

• Note that purely quantum gatescan enable smaller
  circuits
• John A. Smolin, "Five two-bit quantum gates are
  sufficient to implement the quantum Fredkin
  gate, PRA 53(4), 1996, pp. 2855-2856
• Q. Circuit Synthesis via the Ring Normal
  Form(papers by Thomas Beth and Martin Röttler)

41
Why Circuit Libraries?

• Large speedup over straight DFID
• Can be calculated from previous table
• Calculated values are very large
• In practice, the table cannot be generated in
  several hours without circuit libraries
• With libraries, the table takes less than 10 min

42
Outline

• Motivation
• Background
• Theoretical Results
• Synthesis of Optimal Circuits
• An Application to Quantum Computing
• Grovers Search
• Pseudo-classical Synthesis

43
Quantum Circuits

• Necessarily reversible
• Bit-lines are now qubits
• All classical reversible gates still allowed
• Many other gates used as well
• Circuit equivalences for reversible gatesare
  still valid !

44
Grovers Search

• A quantum algorithm for associative search(input
  is not sorted)
• Search criterion a classical one-output function
  f
• Runs in time O(vN)
• classical algorithms require ?(N ) time
• Requires a subroutine that
• changes the phase (sign) of all basis states
  (bit-strings)that match the search criterion f

45
Grover Oracle Circuits

• To change the sign of a bit-string
• Initialize a qubit to 0gt - 1gt
• Compute the classical one-output function f
• XOR the qubit with f
• Whenever f 1, the sign (phase) will change
• Thus, the design of Grover search circuitsfor a
  given f
• Is reduced to reversible synthesis
• Can be solved optimally by our methods

46
Sample Grover Circuit
47
ROM-based Circuits

• Desired circuits must alter phase of basis states
• All bits except one must be restored to input
  values
• Previous work studied ROM-based circuits
• Constraint ROM qubits can never change
• B. Travaglione et al., 2001, http//xxx.lanl.gov/
  abs/quant-ph/0109016
• Theorems heuristic synthesis algorithms
• Our work synthesis of pseudo-classical circuits
• 3 read-only ROM wires that can never change
• 1 wire that can be changed during computation,
  but must be restored by end
• 1 wire on which function is computed

48
Synthesis Algorithms Compared

• Heuristic synthesis of ROM-based circuits
• Proposed by Travaglione et al, 2001
• Based on XOR-sum decomposition (XOR)
• Imposed a restriction at most one control bit
  per gate can be on a ROM bit
• Optimal synthesis (as described earlier)
• with restriction from Travaglione (OPT T)
• without this restriction (OPT)

49
Sizes of 32 ROM-circuits
Size 0 1 2 3 4 5 6 7 8 9 10 11 12
XOR 1 4 6 4 4 12 18 12 6 12 19 16 10
OPT T 1 4 6 4 4 12 21 24 29 33 44 46 22
OPT 1 7 21 35 36 28 28 36 35 21 7 1 0
Size 13 14 15 16 17 18 19 20 21 22 23 24 25 26
XOR 8 10 16 19 12 6 12 18 12 4 4 6 4 1
OPT T 5 1 0 0 0 0 0 0 0 0 0 0 0 0
OPT 0 0 0 0 0 0 0 0 0 0 0 0 0 0
50
Discussion of Empirical Results

• The XOR-SUM heuristic is sub-optimal
• All methods able to synthesize all 256 fns
• OPT T can synthesize as many as OPT
• B. Travaglione et al., 2001
• OPT results symmetrical about 5-6 gates
• Function x requires one fewer gate than 256-x
• Explanation yet to be found
• XOR results symmetrical about 13 gates

51
Conclusions

• Classical reversible circuitsas special-case
  quantum circuits
• Existence theorems
• Reversible De Morgans laws
• Future research on optimization heuristics
• Algorithm for synthesis of optimal circuits
• Applicable to Grovers search
• See details in quant-ph/0207011
• A more detailed version will posted by 09/22

52
Quantum Circuit Synthesisby Simulated Annealing

• Manoj Rajagopalan, Igor L. Markov, and John P.
  Hayes
• Advanced Computer Architecture Laboratory
• University of Michigan, EECS

53
The Problem

• Synthesize a quantum circuit
• Using gates from the given library
• To achieve a specified unitary matrix(can also
  consider effects of measurement)
• Very few qubits are considered
• All matrices are still very small
• Yet, there can be many of gates

54
Synthesis Techniques

• Exhaustive Search
• Matrix Factorization (QR, CS, ILU,KAK)
• Cybenko2000 uses QR
• Dynamic Programming Branch Bound
• ShendePMH2002, quant-ph/0207001
• Genetic Algorithms
• WilliamsG1999, YabukiI2001
• Simulated Annealing this work

55
Simulated Annealing

• Stochastic algorithm
• form of local search for solving optimization
  problems
• Annealing heating and gradual cooling to toughen
  (metal or glass) and reduce brittleness
• Simulated annealing (combinatorial optimization)
• Objective function energy of system
• Minimized by simulating Brownian motion with
  decreasing temperature
• Moves randomly selected, good ones accepted,and
  bad ones accepted in some cases
• Probability of accepting bad move e (-? cost /
  T)

56
Simulated Annealing for Q.S.

• Represent circuit synthesis as an optimization
  problem
• Solution space
• Quantum circuits (circuit topology gate types)
• Constraints
• Output must match specification for given input
• Gates from given library
• Objectives
• Minimize number of gates
• Minimize the error (in some norm)

57
A Naive Annealer Extension

• Consider individual circuits, one at a time
• Evaluate matrix product of all gates
• Compute the error
• Better idea incremental evaluation
• Add/remove/change one gate at a time
• Incrementally compute matrix product

58
Incremental Perturbation

• Perturb gates at ends of circuit
• Effect of adding and removing single gates
  realized by qubit-wise multiplication
• Asymptotic improvement per move
• Suppose we have N gates
• Incremental evaluation O(1) time
• Evaluation from scratch O(N) time

59
Simulated Annealing Procedure

• Initial solution empty circuit (Id matrix)
• Choose initial temperature (), final T 0
• Adopt a temp. schedule (linear, geometric)
• Single-qubit move and CNOT moves
• At either end of current circuit,select (with
  equal probability) from
• No change (NOP)
• Add a gate (ADD)
• Remove a gate (REM)
• Replace a gate (REP)

60
Simulated Annealing Procedure

• Make a random move
• Evaluate error of new circuit
• If error lt10-6, consider synthesis complete
• Else evaluate cost weighted sum of error and
  gates
• If a move improves cost, then accept it
• Else accept move with probability exp (-?cost /
  T)
• Must accept some bad moves to avoid local minima
• T0 means greedy
• Low-temperature annealing cannot climb hills well

61
Simulated Annealing Procedure

• Reduce temp. according to schedule
• Repeat move selection, acceptance
• Perform iterationsuntil final temperature is
  reached

62
Implementation Platform

• AMD Athlon 1.2 GHz processor
• Debian Linux
• C (g v2.95.4 O3)

63
Quantum Gates
64
Test 1 H-X-Z gate circuits

• Hadamard (H), Not (X) and Phase shift (Z)
• Optimal one-qubit circuits typically require up
  to 3 gates per qubit
• Targets for synthesis
• randomly generated circuits with 5 qubits
• Results averagedover 100 independent starts

65
H-X-Z circuit results (5 qubits)
Library Min Size ( gates) Avg Size ( gates) Avg Time (s) Success rate
H X Z 6 17 0.60 100
H X Z½ 7 27 5.53 82
H Z 8 23 1.82 99
H X 10 52 3.48 81
H Z½ 12 29 4.23 81
66
H-X-Z circuit results

• Reasonably small runtimes
• Near-optimal (?) circuits found
• We were not able to find better circuitsby paper
  pencil calculations
• In principle, can change the gate library

67
Test 2 Teleportation circuits(WilliamsG1999
YabukiI2001
Circuits with CNOT gates
R
S
S
L
T
Sender
Receiver
68
Quantum Gates
R Z H H X L H Z X H R L S X Z½ X
69
Synthesis of Sender-Circuit
Gate Library Min Size ( gates) Avg Size ( gates) Avg Time (s) Success Rate
L,CNOT,R 4 53 11.23 95
CNOT,H,X 20 125 31.43 51
CNOT,H,Z 8 162 38.46 45
70
Receiver Circuit Synthesis
Gate Library Min Size ( gates) Avg Size ( gates) Avg Time (s) Success Rate
S,CNOT,T 4 5 0.05 100 (83 opt)
H,CNOT,Z½ 4 6 0.11 100 (68 opt)
H,CNOT,Z½ Z¼, X 3 5 0.22 100 (44 opt)
71
Teleportation Previous Work

• Williams and Gray (Genetic Algos)
• Both circuits with 4 gates, 100 success rate
• Initial population size is 100 circuits
• Requires 4 generations - 2640 circuit evaluations
  - on average
• Yabuki and Iba (Genetic Algos)
• Sender circuit - 4 gates, Receiver - 3 gates
• Simplify the problem by exploiting features
• Requires 350 generations of 5000 candidates on
  average

72
Conclusions

• Simulated annealing
• Promising heuristic for synthesis of q. circuits
• Benefits from incremental evaluation
• Reasonably fast
• Competitive with Genetic Algorithms (better?)
• Flexibility
• Gate libraries can be easily changed(e.g.,
  over-specified)
• Various optim. objectives can be addressed
• Ditto for constraints

73
On-going Work

• More focus on minimizing the number of gates
• So far, mostly tried to find a circuit quickly
• Account for more physical phenomena
• Circuit equivalence up to global phase
• Adaptive move-type selection
• Based on how successful previous moves were
• Temperature schedule, initial temperature
• More challenging synthesis problems
• Add Toffoli gates (increased inter-qubit
  interaction)
• Continuous gate libraries (single-paramater gates)

74
References

1. G.Cybenko, Reducing quantum computations to
   elementary unitary operations, Comp. in Sci. and
   Engin., pp.27-32, March/April 2001.
2. V.V.Shende, A.K.Prasad, I.L.Markov, J.P.Hayes,
   Reversible Logic Circuit Synthesis, to appear
   in Proc. ACM/IEEE Intl. Conf. Comp.-Aided Design,
   Nov. 2002
3. C.P.Williams, A.G.Gray Automated design of
   quantum circuits, In QCQC98 LNCS 1509, pp.
   113-125, Springer-Verlag, 1999.
4. T.Yabuki, H.Iba, Genetic Algorithms for quantum
   circuit design Evolving a simpler teleportation
   circuit-, In Late Breaking Papers at the 2000
   Genetic and Evolutionary Computation Conf., Las
   Vegas, NV, pp. 425-430, 2000.

75
High-Performance Simulation of Quantum
Computation using QuIDDs

• George F. Viamontes, Manoj Rajagopalan, Igor L.
  Markov, and John P. Hayes
• Advanced Computer Architecture Laboratory
• University of Michigan, EECS

76
Problem

• Simulation of quantum computing on a classical
  computer
• Requires exponentially growing time and memory
  resources using standard linear algebra
• Goal Improve classical simulation
• Solution Compress redundancyin relevant
  matrices and vectors

77
Redundancy in Quantum Computing

• Matrix representation of quantum gates contain
  block patterns
• The Tensor (Kronecker) Product
• Create state vectors and operatorsinvolving
  multiple qubits
• Propagates block patternsin vectors and matrices

78
Example of Propagated Block Patterns
Only TWO distinct blocks!
79
Compressed RepresentationsThat Capture Structure

• We could try Lempel-Ziv compression,but
  manipulating compressed data is difficult
• Try using compression based on structurethat we
  understand, e.g.,
• Complex getMatrixElement(int row, int col, int
  qubits) return pow ( sqrt(2) , qubits )
  ( innProdMod2 ( row, col ) ? 1 -1 )
• Still difficult do manipulate
• Consider a decision tree based on row col
• No exponential compression (?)

80
BDDs Data Structures that Exploit Redundancy

• Binary Decision Diagrams (BDDs)exploit repeated
  sub-structure
• Different variants ROBDDs, ZDDs, ADDs, FDDs,
  EVDDs,
• Common idea bottom-up merging of nodes in
  decision trees
• Example f a AND b

f
a
b
Assign value of 1 to variable x
Assign value of 0 to variable x
1
0
81
BDDs Data Structures that Exploit Redundancy

• BDDs have been usedto simulate classical logic
  circuitsLee59, Bryant86
• A circuit can be simulated on all input values
  at once
• BDDs made useful by fast operations
• Bryants main contribution ROBDDs
• A fixed ordering of nodes reduction rules
• Potentially less compression, but faster
  algorithms
• Used in most DD data structures, including
  QuIDDs
• Compare to read-once branching programs

82
Basic BDD Operations Bryant1986

• ( A number of nodes in BDD A )
• Most BDD operations are based on recursive
  procedures ITE, Apply, etc
• Typically take two or three BDDs as arguments
• Apply(A,B) has space and time complexity
• Apply is an algorithmic form of Booles Expansion
• Different types of DDs optimize operationsfor
  specific contexts and reduction rules, e.g.,
• EVDDs (edge-valued), ZDDs (zero-suppressed), etc

83
Linear Algebra via BDDs

• Variants of BDDs have been used to represent
  matrices and vectors
• Algebraic Decision Diagrams (ADDs) treat variable
  nodes as matrix indices Bahar93
• ADDs compress repeated block patterns in matrices
  and vectors
• Linear Algebraic operations can be performedas
  ADD traversals (i.e., w/o decompression)
• From general to specific
• MTBDDs ? ADDs ? QuIDDs

84
Quantum Information Decision Diagrams

• Quantum Information Decision Diagrams (QuIDDs)
• An application of ADDsto the quantum computing
  domain
• Similar structure to ADDs
• Three types of nodes
• Row, Column, Terminal
• Use modified ADD operations

85
QuIDD Structure

• BDD variable ordering
• Defines the order in which different node types
  appear
• QuIDD variable ordering interleaves row and
  column variables
• Terminal nodes are always last

86
Quantum Circuit Simulation Issues Specific to
QuIDDs

• Use state-vector representation
• In principle, QuIDDs can also modelthe
  density-matrix representation
• Avoid matrix-matrix mult. (for efficiency)
• Tensor products and matrix-vector multiplications
  are performed
• Are very efficient

87
QuIDD Vectors

• Use column and terminal variables
• Represent qubit state vectors
• Some examples

T
T
f
f
00
00
01
01
10
10
11
11
88
QuIDD Matrices

• Use row, column, and terminal variables
• Represent gates / unitary matrices
• There is no requirement for unitary matrices,
• Constant factors can be stored separately

89
Example 2-Qubit Hadamard QuIDD
f
10
01
11
00
00
01
10
11
90
QuIDD Operations

• Based on the Apply algorithm Bryant1984,ClarkeEtA
  l1996
• Construct new QuIDDs by traversing two QuIDD
  operands
• Perform op at terminals (op can be , , etc.)
• The variable ordering directs the traversal
• General Form f op g where f and g are QuIDDs,
  and x and y are variables in f and g, respectively

91
Tensor Product

• To compute A? B
• Every element of a matrix Ais multiplied by the
  entire matrix B
• QuIDD implementation uses Apply
• Operands are A and B
• Variables of operand B are shifted
• op is defined to be multiplication

92
Matrix Multiplication

• A modified form of the Apply function
• Dot-product can be done on QuIDDs without
  decompression
• Skipped nodes are counted
• A factor of 2skipped is multiplied by
  dot-products
• QuIDD Implementation
• Modified ADD matrix multiply algorithm Bahar93
• Support complex number terminals
• Account for row/column variable ordering

93
Other Operations

• Matrix addition
• Call to Apply with op set to addition
• Scalar operations
• A special one-operand version of Apply
• Qubit measurement
• A combination of matrix multiplications,tensor
  products, and scalar operations

94
Simulation of Grovers Algorithm

• QuIDDPro was tested by running instances of
  Grovers Algorithm
• Results indicate linear memory usage in many
  cases
• Any circuit with an oracle whose QuIDD form is
  polynomial in of qubits

95
Sample Circuit Representation
H
H
H
Oracle
Conditional Phase Shift
0gt
H
H
H
0gt
. . .
. . .
. . .
H
H
1gt
96
Simulation of Grovers Algorithm

• iterations computed BoyerEtAl96
• iterations
• Where
• M of solutions, 2q of elements in data set
• Exponential runtime on a quantum computer
• When M is small, the number of iterationsis
  exponential in the number of qubits

97
Projected Grover Iterations

• SANITY CHECK Make sure that the number of
  iterations predicted by Boyer et al. results in
  the highest probability of measuring the item(s)
  to be searched

98
Experiment versus Predictions
99
Simulation Results forGrovers Algorithm

• Linear growth of QuIDDs in Grovers algo
• Number of nodes in QuIDDs shown

100
Grovers Algorithm Results using Oracle 1

• Oracle 1 searchesfor one element in the data
  set
• Oracle polynomial in size
• Linear memory asymptotics
• Run-times are extremely low vs Matlab

101
Grovers Algorithm Results using Oracle 1
Linear growth with QuIDDPro
102
Grovers Algorithm Results using Mod-1024 Oracle

• Finds elements in the data set whose 10 least
  significant bits are 1
• Useful in demonstrating asymptotics
• Memory and runtime are governed purely by the
  size of the system

103
Grovers Algorithm Results using Mod-1024 Oracle

• For data up to n25 qubits,linear least-squares
  regressionshows that memory (MB) grows as
  7.5922 0.0410n

Linear growth with QuIDDPro
104
Conclusions and Future Work

• Asymptotic performance whenQuIDD form of oracle
  is poly-sized
• QuIDDPro 1.66n Ideal Q. Computer 1.41n
• Far more efficient than other classical
  simulation techniques
• MATLAB, Blitz ?(2n)
• We plan to simulate other algorithmsusing QuiDD
  Pro ( inject errors)
• A simulation of Shors algorithm operational
• Details in quant-ph/0208003

105
References

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  Circuits by Binary Decision Diagrams, Bell
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• 2 R. Bryant, Graph-Based Algorithms for
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  Computers, vol. C-35, pp. 677-691, Aug 1986.
• 3 R. I. Bahar et al., Algebraic Decision
  Diagrams and their Applications, In Proc.
  IEEE/ACM ICCAD, pp. 188-191, 1993.
• 4 E. Clarke et al., Multi-Terminal Binary
  Decision Diagrams and Hybrid Decision Diagrams,
  In T. Sasao and M. Fujita, eds, Representations
  of Discrete Functions, pp. 93-108, Kluwer, 1996.
• 5 M. Boyer et al., Tight Bounds on Quantum
  Searching, Fourth Workshop on Physics and
  Computation, Boston, Nov 1996.