DIGITAL%20INTEGRATED%20%20%20%20ELECTRONICS

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DIGITAL INTEGRATED ELECTRONICS
55144
Lecture 8
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Nonlinear Load Line
A plot of the load constraint on the transistor
characteristics. Helps us visualize possible
operating points. When Vin is given, a locus of
operation is known Load line identifies a point
on this locus. Gives meaning to VTC. Helps us
compare various kinds of loads with little effort.
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Nonlinear Load Line

• A good old change in variables!

The change in voltage variable has two steps 1.
VR -VDS, a reflection about the current axis,
and 2. translation to the right by VDD.
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Load Lines Linear and Nonlinear
When Vin lt VT0, cutoff, therefore VOH VDD Next,
transistor operates in saturation. Finally in
linear region.
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Inverter with Saturated Enhancement Load
Load has body effect Largest for high Vout
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In the transition region, both transistors are
saturated. Ignoring body effect,
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Inverter with Linear Enhancement Load
Load has body effect Separate supply for
gate Connect gate to VDDVT0 This gives
borderline linear operation
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Inverter With Depletion Load
Body effect! VSB Vout B. E. and channel-l
modulation change the curve.
We expect a narrow transition region
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Depletion-Load Inverter Mathematical Analysis
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VTC for Depletion Load Inverter
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4
3
2
3
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Clearly satisfied by VOH VDD
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Passes through (Vin, Vout) (VT0,VDD)
No Vout term!
Note Load transistor has body effect. We
eventually need to use VT,loadVT,load(Vout)
VT,load becomes less neg. as Vout increases.
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Body effect and channel-length modulation change
Region 3
VT,load becomes less negative as Vout increases.
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Region 4
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Critical Points of Depletion-Load Inverter VOL
For Region 4
Iteration required, but not so bad if constants
are known
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Critical Points of Depletion-Load Inverter VIL
For Region 2
Differentiate with respect to Vin.
VT,load does not change much at high values of
Vout.
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Critical Points of Depletion-Load Inverter VIL
Ignoring body effect, locates VIL at intersection
of straight line and region 2 curve. Requires
simultaneous solution for VIL. Including body
effect requires iteration.
Straight line is replaced by a curve.
Eliminate Vout, substitute Vin VIL.
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Critical Points of Depletion-Load Inverter VIH
For Region 4
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Finding VIH (ctd.)
Again, an equation.
see (5.44)
Ignore body effect change in VT,load.
Again necessary to find intersection of dashed
straight line with parabolic region 4 curve, i.e.
Eliminate Vout and change notation to Vin VIH.
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Finding VIH (ctd.)
Textbook solution without ignoring body effect.
Result is an implicit funtion of Vout vs. Vin,
which replaces the straight line on the preceding
page. Solving this iteratively with the region
4 curve gives convergence to Vin VIH.
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Depletion Inverter Design Parameters
The most important static design parameter is kR,
defined by
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Compared to the enhancement-load circuit of page
6, smaller transition region is possible with
smaller transistor size disparity.
resistive
enhancement
...area occupied by depletion-load inverter
circuit with an acceptable circuit performance is
expected to be much smaller than the area
occupied by a comparable resistive-load or
enhancement-load inverter.
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Depletion-Load Inverter Layout
Drain of driver and source of load share n
diffusion region. Donor implant reduces VT0 of
the load.
Driver-to load ratio is about 4 giving good VTC.
Overall, a fairly compact inverter structure.
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Depletion-Load Inverter Layout 2
Buried contact reduces size gate in direct
contact with n source second contact window to
gate eliminated
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Depletion-Load Inverter Analysis Example
Find VOH, VOL, VIL, VIH
Find VOL
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VOL Iterations
Textbook answer 0.186 V
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Find VIL
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Find VIL (Ctd.)
Guess
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Find VIL (Ctd.)
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Average Power Dissipation
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Thats all folks