OCAPI

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OCAPI
EE213A
Spring 2000
Prof. Ingrid Verbauwhede
http//www.imec.be/ocpai/

• Maged Attia(mattia_at_ucla.edu)

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Agenda

• Introduction to OCAPI
• Case Study
• Complete Design Flow of FIR
• Homework
• Design of LFSR

(Wednesday)
(Friday)
(Friday)
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Introduction to OCAPI
Outline

• OCAPI vs. ART Designer
• How does OCAPI work?
• OCAPI Classes
• Design Cycle in OCAPI
• Compiling C/OCAPI
• Introduction to the case study.

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OCAPI vs. ART Designer
OCAPI
Art Designer
1) C based
1) C/C based
2) Bit Parallel
2) Bit Parallel Arch.
3)
3)
4) More flexible
4) More friendly
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How does OCAPI Work?
qlib.h
include
C
OCAPI
Description
Classes
libqlib.a
Link
Add
C Compiler
Mult
Ram
Sub
Run
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OCAPI Classes 1- Fixed Point
dfix a dfix a(0.25) dfix a(0.25, 10
,8) dfix a(0.25, 10, 8, tc, st, rd) tc
twos complement ns unsigned wp for
wrap-around st saturation fl for
truncation rd rounding
Default
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OCAPI Classes 2- IN/OUT
I
O
a
b
TX
queue
in.dat
queue
out.dat
dfix a FB I(I) src a(a, I, in.dat)
dfix b FB O(O) snk b(b, O, out.dat)
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OCAPI Classes 3- Internal Signal
_sig a(a) plain signal
with fl-p inside it _sig b(b, dfix(0, 10, 8)
plain signal with fx-p inside it _sig
k(0.5) Clk ck
Registered signal C with initial _sig c(c, ck ,
k) value k
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OCAPI Classes 4- FSM
ctlfsm f Creat FSM F ltlt
my_fsm Give it a name State rst
State active Rst ltlt
my_rst Active ltlt my_active F ltlt deflt(rst)
Tell which one is the default Active
ltlt allways ltlt active Active ltlt _cnd(a) ltlt rst
Creat 2 states
Give them name
Transitions
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Design Cycle in OCAPI

• Un-Timed Design
• - Easy and fast to design
• - Non implementable
• - Real description
• Timed Design
• - Implementable

Timed
Timed
Un-Timed
TX
RX
Channel
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Design cycle in OCAPI
1) Un-timed Design
Refine
Non implementable Fixed point EASY
Description !!!!!!
Function Description
Refine
Word-length
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Design cycle in OCAPI
Void addadd( int in1 int in2
int out ) out in1
in2 return 0
Void main() Add Add(a, b, c)
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Design cycle in OCAPI
Void addadd( dfix in1 dfix in2
dfix out ) if ( (
in1.getsize() lt1) (..) ) return 0
out in1.get() in2.get() return 1
Refine
Void main () FB a(a) . Src
src1(src1, a, src1) .. systgen S1(S1)
S1 ltlt src1 S1 ltlt src2 S1.next ltlt Add
..
Void main() Add Add(a, b, c)
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Design cycle in OCAPI
Everything is the same but instead of
dfix Use dfix ( , w, l, )
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Design cycle in OCAPI
2) Timed Design
Refine
Function Description
C/OCAPI
Refine
Fixed/FSM
Word-length
Auto
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Design cycle in OCAPI
FSM and FG
Void addadd( dfix _in1 dfix
_in2 dfix _out )
ctrlfsm _fsm Sfg _add State _go _fsm ltlt
deflt(_go) _go ltlt allwaysltlt _addltlt_go
Void main () FB a(a) . Src
src1(src1, a, src1) .. systgen S1(S1)
S1 ltlt src1 S1 ltlt src2 S1.next ltlt Add
..
Clk ck Int I For (I0 Ilt3 I) S1.run(clk)
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Compiling C/OCAPI
C
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Compiling C/OCAPI
C/OCAPI
VHDL
C
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Introduction to the case study
Step 1 Specifications -gt Coefficients Step 2
Create floating point description for the whole
system. Step 3 Create fixed point description
for the UPS and the FIR and refine for best word
length Step 4 Use that WL to create fx-p FSM
description and run timed simulation to generate
the VHDL code.