Electronic Testing Education, Research and Training Infrastructure

1
Electronic Testing Education,Research and
Training Infrastructure

• NSF Computing Research Infrastructure (CRI)
  Project at Auburn University
• Vishwani Agrawal
• vagrawal_at_eng.auburn.edu

2
A Test Lab Infrastructure Project

• Objective Establish a modern VLSI test Lab at
  Auburn for
• Teaching Include testing in university courses.
• Research Conduct leading-edge research.
• Training Develop training facilities for
  industry.
• Collaborators Auburn (5), Alabama-Tuscaloosa
  (1), Alabama-Huntsville (1), Tuskegee (2).
• Funding NSF, 1.1M (600k, Auburn), Oct/07
  Sep/10.

3
Principal Investigators

• Auburn University
• Vishwani Agrawal
• Foster Dai
• Vic Nelson
• Adit Singh
• Chuck Stroud
• University of Alabama in Huntsville
• Rhonda Gaede
• University of Alabama Tuscaloosa
• Bruce Kim
• Tuskegee University
• Hira Narang
• Muhammad Ali
• Chung-Han Chen

4
Proposed Tasks

• VLSI test laboratory at Auburn.
• To be established in collaboration with the
  three other universities. The facility will be
  available to remote users via networking.
• Test lab applications.
• Applications for inclusion in university
  curricula. These will include experiments on
  testing of digital, analog and RF chips, FPGAs
  and system-on-chip devices, and on methods for
  assessing yield and reliability of devices.
• Training Classes.
• Industry-oriented training with hands-on test
  lab exercises.
• Research.
• Silicon debug methods, ATE-based formal
  verification, mixed-signal and RF circuit
  testing, SOC testing, FPGA testing, and
  non-redundant and parallel architectures for
  improving yield and reliability. Develop Silicon
  benchmarks, circuits with fault-injection
  capabilities, that will be made available to
  researchers working on debug methods.

5
Vision of the Project
6
Subtask Infrastructure Matrix
Subtasks Infrastructure test set ups Infrastructure test set ups Infrastructure test set ups Infrastructure test set ups Infrastructure test set ups Infrastructure test set ups Infrastructure test set ups Infrastructure test set ups
Subtasks ATE Silicon benchmarks Digital Mixed-signal Memory RF FPGA SOC
VLSI Design Course v v v
Adv. VLSI Des. Course v v v
VLSI Testing Course v v v
New Testing Courses v v v v v v v v
Industrial Courses v v v v v v v v
Silicon Debug Res. v v v
Silicon Verification v v v
RF BIST research v v v
Timing Yield research v v v
Reliable architectures v v v v
FPGA testing res. v v v v
7
Project Status January 2009

• Proposal submitted in November 2006.
• Proposal revised in August 2007.
• Awarded October 2007.
• Year 1 progress report submitted and approved in
  August 2008.
• Order placed for T2000GS in September 2009
• Year 2 plan
• ATE installed and running (Delivery expected in
  Feb 2009)
• Develop classroom experiments on digital test