AVR Data Representation

1
AVR Data Representation

• Assembly Language Programming
• University of Akron
• Dr. Tim Margush

2
Data Representation

• Information must be stored in a binary code to be
  manipulated by the computer
• Data should be represented efficiently
• Easy to translate for I/O
• Easy to manipulate internally
• Space efficient and accurate

3
Types of Data

• Numeric
• Requires at least n bits to represent 2n distinct
  numbers
• Several common representations are used
• Efficiency? Processor supports limited formats
• Accuracy? Floating point approximations

• Boolean
• Requires 1 bit to distinguish between values
• Typically 0 false, 1 true
• Efficiency? Instruction support for bit access?
• Character
• ASCII?
• Efficiency? ASCII is a 7-bit code
• Other data types?

4
Unsigned Integer

• Fundamental numeric representation is for
  unsigned integers
• A fixed size container is used
• Byte, word, etc. provides 28, 216, etc.
• Utilizes the natural correspondence between
  binary contents of the container and binary
  representation of the integer
• AVR is little-endian, storing the least
  significant byte first

5
Truncation

• An n-bit container allows unsigned data from 0
  through 2n-1 to be accurately represented
• Truncation occurs when a value too large for a
  container is stored
• Truncation in this context means the
  most-significant bits are thrown away
• Mathematically, truncation is equivalent to a mod
  operation
• Storing k as an n-bit unsigned integer results in
  the value k 2n being stored

6
Unsigned Data in Assembly

• Unsigned data can be used in immediate mode
  instructions
• ldi R16, 37
• ldi R30, F0
• Unsigned data can be assembled to memory
• .db 0252 only in flash or EEPROM
• .dw 65535
• .db 23 87 truncation occurs

7
Support

• All ALU's provide support for arithmetic
  operations on unsigned data
• Generally, an overflow or illegal subtraction is
  indicated by the carry flag
• The AVR provides the following instructions for
  unsigned integers
• ADD, ADC, ADIW, SUB, SUBI, SBC, SBCI, SBIW, MUL,
  and FMUL

8
Character

• Characters are generally represented using their
  ASCII code with a leading 0 added to fill out a
  byte
• Unicode is becoming popular for general purpose
  computing systems and is important in the
  microcontroller market to support international
  applications
• Character data is a special case of unsigned
  integer
• The AVR processor supports characters as unsigned
  integers
• The AVR Assembly supports ASCII translation,
  recognizing literals for any ASCII code ('a',
  '', )

9
Signed Integers

• Several representations are used
• Two's Complement
• One's Complement
• Excess-n or Biased
• Sign and Magnitude
• BCD
• Most processors provide direct support for Two's
  Complement numbers

10
Two's Complement

• Fixed size code n bits (usually 8, 16, )
• Legal range is -2n-1 through 2n-1-1
• The non-negative numbers use the unsigned code
• The leading bit is therefore 0
• The rest of the codes are assigned to the
  negative numbers

0 1 2 126 127 -128 -127 -126 -3 -2
-1 00 01 02 7E 7F 80 81 82 FD FE FF
11
Encoding Rules

• To determine the two's complement code for a
  signed integer
• Convert the magnitude (absolute value) of the
  integer to binary
• Add leading zeros to fill the container
• If the number was negative, apply the change sign
  rule
• Flip the bits to the left of the rightmost 1

12
8-bit Examples

• 47
• 47 in binary is 101111, so 00101111 (done)
• -47
• extra step to change the sign yields 11010001
  (flipped 7 bits)
• -128
• 128 in binary is 10000000, and the change sign
  rule yields 10000000 (no change)
• 128
• This is out of range, 127 is the largest possible

13
Complements

• Complementary implies two parts that make up a
  whole
• Complementary angles add to 90 degrees
• Complementary colors add (mix) to get grey
• The n-bit, two's complement codes for x and x
  are complementary in this sense
• They always add to 2n

47 and 47
14
Change Sign Rule

• There are three common ways to describe this rule
• Flip all the bits to the left of the rightmost 1
• Flip all the bits, then add 1
• Subtract from 2n (assuming an n-bit code)
• Each method gives the same result

15
Two's Complement in Assembly

• Two's complement is the AVR native signed integer
  format
• ldi R16, -37
• subi R16, -128
• .dw -32000
• .db -500 truncated

16
ADD Rd, Rr

• The AVR add instruction combines two bytes in a
  way that is consistent with addition of numbers
• Use this instruction for unsigned or signed
  (two's complement) data
• There is no distinction between these two data
  types when adding
• Add Rd, Rr simply adds the register contents as
  if they were unsigned integers
• The sum is truncated if necessary and stored in Rd

17
SUB Rd, Rr

• The AVR add instruction combines two bytes in a
  way that is consistent with subtraction of
  numbers
• Use this instruction for unsigned or signed
  (two's complement) data
• There is no distinction between these two data
  types when subtracting
• Sub Rd, Rr performs the operation Rd Rd Rr,
  treating the register contents as if they were
  unsigned integers
• The difference is truncated if necessary

18
Status Register

• 6 bits of SREG are affected by ADD
• Ex. 58 155 213 or 58 (-101) (-43)

00111010 00111010 Rd 10011011 Rr ----------
11010101 R
H (Rd3Rr3)(!R3(Rd3Rr3)) S NV V
(Rd7Rr7!R7)(!Rd7!Rr7R7) N R7 Z
!R7!R6!R0 C (Rd7Rr7)(!R7(Rd7Rr7))
1 1 0 1 0 0
19
H, N and C

• Half-carry and Carry are just the carry bits
• Negative is bit 7 sign of the result

00111010 00111010 Rd 10011011 Rr ----------
11010101 R
H (Rd3Rr3)(!R3(Rd3Rr3)) S NV V
(Rd7Rr7!R7)(!Rd7!Rr7R7) N R7 Z
!R7!R6!R0 C (Rd7Rr7)(!R7(Rd7Rr7))
1 1 0 1 0 0
20
V and Z

• oVerflow is 1 when carry into bit 7 is different
  from carry out of bit 7
• This indicates signed overflow
• Z is 1 when all bits of result are 0

00111010 00111010 Rd 10011011 Rr ----------
11010101 R
H (Rd3Rr3)(!R3(Rd3Rr3)) S NV V
(Rd7Rr7!R7)(!Rd7!Rr7R7) N R7 Z
!R7!R6!R0 C (Rd7Rr7)(!R7(Rd7Rr7))
1 1 0 1 0 0
21
S (Signed Result Sign)

• The Sign flag represents the sign of the correct
  result after a signed add or subtract
• S an N are identical if no overflow occurs (V0)
• When overflow occurs (V1), the calculated result
  will have the wrong sign
• In this case, S is !N
• Both cases are handled with the single logical
  result
• S NV

• -2 - 127 is -129
• ALU outputs 127 so N0
• Overflow so V1
• NV is 1 (sign is -)
• 127 (-1) is 128
• ALU outputs -128 so N1
• Overflow so V1
• NV is 0 (sign is )
• 64 63 is 127
• ALU outputs 127 so N0
• No Overflow so V0
• NV is 0 (sign is )

22
Status Register and SUB

• 6 bits of SREG are affected by SUB
• Ex. 179 - 96 83 or -77 - (96) (-173)

01000000 10110011 Rd -01100000 Rr ----------
01010011 R
H (!Rd3Rr3)(R3(!Rd3Rr3)) S NV V
(Rd7!Rr7!R7)(!Rd7Rr7R7) N R7 Z
!R7!R6!R0 C (!Rd7Rr7)(R7(!Rd7Rr7))
0 1 1 0 0 0
23
H, N and C

• Half-carry and Carry are borrow indicators
• Unsigned interpretation CRdltRr?10

01000000 10110011 Rd -01100000 Rr ----------
01010011 R
H (!Rd3Rr3)(R3(!Rd3Rr3)) S NV V
(Rd7!Rr7!R7)(!Rd7Rr7R7) N R7 Z
!R7!R6!R0 C (!Rd7Rr7)(R7(!Rd7Rr7))
0 1 1 0 0 0
24
V and Z

• oVerflow is 1 when borrow from hypothetical bit 8
  is different from the borrow from bit 7
• This indicates signed overflow

01000000 10110011 Rd -01100000 Rr ----------
01010011 R
H (!Rd3Rr3)(R3(!Rd3Rr3)) S NV V
(Rd7!Rr7!R7)(!Rd7Rr7R7) N R7 Z
!R7!R6!R0 C (!Rd7Rr7)(R7(!Rd7Rr7))
0 1 1 0 0 0
25
Binary Borrowing
44-(-73) or 44-183
26
Binary Borrowing
44-(-73) or 44-183
27
Binary Borrowing
44-(-73) or 44-183
28
Binary Borrowing
44-(-73) or 44-183
We borrow making this column 10 - 1
110111 00101100 -10110111 --------- 110101
10
A borrow will be needed here
1110111 00101100 -10110111 --------- 1110101
11110111 00101100 -10110111 --------- 01110101
The 0 becomes a 1 (note this was already borrowed
from)
1
1
Borrow again
29
Binary Borrowing Flags

• 11110111
• 00101100
• -10110111
• ---------
• 01110101

• H 0
• no borrow from b4
• S 0
• signed result gt0
• V 0
• signed result correct
• N 0
• not negative
• Z 0
• not zero
• C 1
• illegal unsigned subtraction
• i.e. a borrow to calculate bit 7

44-(-73) 117 or 44-183 117 (illegal)
30
Subtract Immediate

• SUBI Rd, K performs Rd Rd-K
• Immediate means the operand is encoded directly
  in a field of the instruction
• K is any signed or unsigned byte
• Rd is one of R16 through R31 (not R0-R15)
• Flags and results are the same as if K were in a
  register (Rr) and SUB Rd, Rr were executed

31
Add Immediate

• There is no such instruction
• To add any number K to a value in Rd, use this
• SUBI Rd, -K
• (The flags will be set according to the
  subtraction)

32
ADIW, SBIW

• ADIW Rd1Rd, K
• SBIW Rd1Rd, K
• Add/Subtract Immediate to/from word
• Only allowed for upper 4 register pairs
• Use R25R24, XHXL, YHYL, or ZHZL
• K is 0-63

R27R26
R29R28
R31R30
33
ADIW, SBIW Flags

• Flags are similar to those of ADD and SUB
• H is unaffected by these operations
• V is set if the sign of the result is different
  from the original value (signed overflow)
• N depends on bit 15 (High byte, bit 7)
• C is the carry out of (or borrow into) the high
  byte

34
ADIW, SBIW Timing

• These instructions require 2 clock cycles
• They are essentially a shortcut for a sequence of
  two instructions
• Except that the flags are slightly different

adiw ZHZL, K answer is equivalent to subi ZL,
-Ksbci ZH, FF
sbiw ZHZL, K answer is equivalent to subi ZL,
Ksbci ZH, 0
35
ADC, SBC, and SBCI

• These instructions are designed to support
  multi-byte addition and subtraction where the
  carry flag is set by a previous operation
• ADC Rd, Rr adds the carry flag into the usual sum
• Rd Rd Rr C
• SBC Rd, Rr borrows from Rd (if C1) before
  subtracting
• Rd (Rd C) - Rr
• SBCI Rd, K performs Rd (Rd-C) K
• Rd is one of R16 through R31, K is any byte

36
Word vs Byte

• When add/subtract immediate word is used, the Z
  flag is set according to the 16-bit result
• When SBC and SBCI are used, the Z flag depends on
  the 8-bit result AND the previous Z flag
• When ADD, SUB, and ADC are used, the Z flag is
  set according to the 8-bit result.

37
Word Addition

• Adding two word values requires two steps
• Add the low bytes as if they were unsigned data
• ADD works well here
• Add the high bytes taking into account the carry
• ADC is the perfect instruction here

38
Programming
Example 7325 80F1 Unsigned 29477 33009
62486 Signed 29477 (-32527) -3050

• .equ A 7325
• .equ B 80F1
• .def AH R17 Name 16-bit registers
• .def AL R16
• .def BH R19
• .def BL R18
• ldi AH, high(A) load A into register(s)
• ldi AL, low(A)
• ldi BH, high(B) load B into register(s)
• ldi BL, low(B)
• add AL, BL add B low
• adc AH, BH then high
• result is in AHAL

39
Executing

• ADD R16,R18
• 25F1 16 and C1
• ADC R17,R19
• 7380C F4
• Note that V and C are 0
• no overflow (signed or unsigned)
• S and N are 1
• indicating a negative result
• R17R16 is F416
• Unsigned 62486
• Signed -3050

40
INC and DEC

• INC Rd
• Signed increment Rd
• DEC Rd
• Signed decrement Rd--
• Warning these affect only S, V, N, and Z
• No change to H or C
• FF increments to 00 (and 00 decrements to FF)
  but C remains unchanged (think signed integers)
• INC/DEC between 7F and 80 sets V to indicate
  signed overflow has occurred

41
One's Complement

• Fixed size code n bits
• Legal range is -2n-1-1 through 2n-1-1
• The non-negative numbers use the unsigned code
• The leading bit is therefore 0
• The code for a negative number is obtained by
  complementing the code for its magnitude

0 1 2 126 127 -127 -126 -125 -2 -1
-0 00 01 02 7E 7F 80 81 82 FD FE FF
42
One's Complement Examples

• 47
• 47 in binary is 101111, so 00101111 (done)
• -47
• extra step to change the sign yields 11010000
• -0
• 0 is 00000000, so -0 is 11111111, an oddity in
  this system
• -127
• 127 is 01111111, so the correct code for -127 is
  10000000

43
Sign and Magnitude

• Fixed size code n bits
• Legal range is -2n-1-1 through 2n-1-1
• The non-negative numbers use the unsigned code
• The leading bit is therefore 0
• The change sign rule is simply flip the leading
  bit

0 1 2 126 127 -0 -1 -2 -125 -126
-127 00 01 02 7E 7F 80 81 82 FD FE
FF
44
SM Examples

• 47
• 47 in binary is 101111, so 00101111 (done)
• -47
• extra step to change the sign yields 10101111
• -0
• 0 is 00000000, so -0 is 10000000, an oddity in
  this system
• -127
• 127 is 01111111, so the correct code for -127 is
  11111111
• Note that the magnitude is always obvious in this
  scheme

45
Excess-N

• Fixed size code n bits
• Legal range is -2n-1 through 2n-1-1
• Each integer is biased by 2n-1 and then encoded
  as an unsigned value
• Use the two's complement change sign rule

Biased by 128
-128 -127 -126 -2 -1 0 1 2 125 126 127
00 01 02 7E 7F 80 81 82 FD FE FF
46
Excess-128 Examples

• 47
• 47128 175 in binary is 10101111 (done)
• -47
• -47128 81 in binary is 01010001 (leading zero
  added)
• 0
• 0 128 gives 10000000
• -128
• -128128 0, so 00000000
• Note that negative numbers have a leading zero,
  non-negative numbers start with 1

47
Binary Coded Decimal

• Each digit of the base ten numeral is stored
  using its natural 4-bit code
• Digit values 1010 through 1111 are not legal
• The digit codes are stored in consecutive storage
  locations
• They may be stored two per byte (Packed BCD) or
  one per byte

48
Binary Coded Decimal

• BCD Values may be in fixed size containers, or a
  special code may indicate the end of the digit
  list
• The unused nybble codes can be employed to
  indicate a sign
• Example 1100 and 1101 -
• If the sign nybble is placed at the end of the
  list of digits, it serves as the end-of-number
  sentinel

49
BCD Advantages

• The primary advantage of BCD is I/O
• Translating between a BCD coded integer and a
  string of ASCII digits is as easy as adding or
  subtracting '0'
• '7' '0' 07
• 03 '0' '3'
• Packing and unpacking between nybbles and bytes
  is very easy as well

50
BCD Disadvantages

• Most processors do not support BCD arithmetic
• The H flag can be used to implement BCD
  arithmetic algorithms
• Arithmetic is slowed by multi-digit calculations
• Unused bit combinations means some space is
  wasted by this representation

51
BCD Example

• 473
• Unpacked format 04 07 03
• Packed format 04 73
• 1095
• Unpacked format 01 00 09 05
• Packed format 10 95

52
Data in Programs

• Initialized memory
• Use the define byte/word/ to cause the assembler
  to preset bytes in EEPROM and flash
• This hardware does not allow initialized RAM
• There is no "loader"
• Make good use of expressions
• .db -1 is probably better than .db 0xFF
• .db (1ltlt5)(1ltlt 4) might be better than .db 30

53
Assignment Statements

• Programming in high-level languages makes us take
  simple statements such as
• sum ab
• You cannot translate this to anything like
• ldi sum, ab
• The first ab will be evaluated at run time the
  second ab, at assembly time

54
So?

• ldi sum, ab means load the register named sum
  with the value of the expression ab.
• Assume sum is a register and a and b are labels
  of bytes in memory (variables)
• The expression, ab, means add the values, but
  the values of labels are their addresses.
• The load immediate will load the sum of the two
  addresses into sum ?

55
Implementing an Assignment

• Think of every step needed in the calculation
• Use registers to hold the intermediate values and
  working data
• Store the result

• ab
• Load value at a into a register
• Load value at b into another register
• Add the two values
• sum expValue
• Store the result into the destination

56
Variables

• Variables are concepts in assembly languages
  they are not syntax
• a .byte 1 a is not a variable
• Labels on memory locations represent the address
  of the memory, not the value stored in memory
• int x 3 //the "variable" x represents the
  value at runtime
• The label a represents the address of a byte at
  runtime (and at assembly time)

57
More About Memory
32-bit data

• Java
• int sum, a, b
• sum ab

• AVR Assembly
• .dseg
• sum byte 1
• a byte 1
• b byte 1
• .cseg
• lds R16, a
• lds R17, b
• add R16, R17
• sts sum, R16

8-bit data

• lds loads a register from a byte of memory
• sts stores the byte from a register into memory
• memory in this case means SRAM

58
Allocation or Instantiation

• This is the process of setting aside memory for
  the encoded data
• .byte sets aside uninitialized memory
• .db (and others) sets aside and initializes
  memory
• In assembly language, variables sometimes "live"
  in registers
• .def R10 sum

59
Memories

• Non-volatile memory
• Flash is used to hold constant data needed by the
  program
• EEPROM can be used for constant data, or data
  that changes occasionally
• Volatile memory
• SRAM can be used for any type of data, but must
  be initialized during execution

60
Storage Allocation

• Static variables
• Assigned to a specific location for the duration
  of the program
• Allocation is determined by the assembler
• Non-static variables
• Assigned to a location during execution
• The location may change at any time
• Allocation is managed by the program

61
Branching

• Jump and branch instructions are used to
  implement control structures (repetition and
  selection)
• In the AVR context, branches are conditional
• The branch is taken only if some condition is
  true
• The only supported conditions are the values of
  the 8 bits in the status register

62
Branch if Not Equal

• The decrement instruction DEC affects the Z flag
• The conditional branch BRNE alters the natural
  sequential flow IF the zero flag is clear
• brne branches (back to lp) or
• sequences (to the next instruction in program
  memory)

• ldi R16, 10
• lp
• inc R20
• dec R16
• brne lp
• out PORTB, R20

How many iterations will occur? What appears at
PORTB?