Silicon Substrate for LEDs

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Light Emitting Diode (LED) Substrates Ken
Polasko Arizona Technology Enterprises
(AzTE) SkySong 1475 North Scottsdale Road, Suite
200 Scottsdale, AZ 85257
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Silicon Substrate for LED Growth

• Lighting and Light Emitting Diodes (LEDs)
• Light emitting diode (LED) technology is
  positioned
• to capture significant market share.
  The 2006
• market for high-brightness LED exceeded
  4B with a CAGR of 15.
• LEDs are poised to make dramatic reduction in
  global energy consumption
• The US Department of Energy estimates
• potential global savings of 100B/yr
  and
• corresponding reductions of carbon
• emissions of 200 million tons/yr by
  2025.
• By 2025, 50 efficient LEDs could cut global
  lighting energy usage by 50 and total
  electricity usage by 10.

Innovation ZrB2 Buffer Layer

• Growing a zirconium diboride (ZrB2) buffer layer
  enables the growth of high quality GaN on a
  relatively inexpensive Si substrate
• ZrB2 is lattice matched to GaN enabling high
  quality material
• Enables the replacement of a high cost substrate
  with a much lower substrate cost by 10x
• Three patents filed

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Silicon Substrate for LED Growth
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Silicon Substrate for LED Growth
Market Opportunities

• Lighting
• Incandescent replacements
• Fluorescent replacements
• Automotive lighting
• Fixed mobile display back lighting
• Cell phone camera flash lighting
• General illumination
• Lasers e.g. Blu-ray
• Medical sterilization, imaging,
  skin therapy
• Industrial curing
• Research instruments
• Detectors

• Electronic Devices
• High-power devices
• High-frequency devices
• High-temperature devices
• Telecommunication base
• station power amplifiers (PAs)
• WiMax base station PAs
• Power inverters e.g. solar
• Photonic devices integrated on Si CMOS

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Silicon Substrate for LED Growth
Competition
Luminous Efficiency (lumens / watt)
Source Lumileds
Source Lumileds
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Silicon Substrate for LED Growth

Problem Expensive LEDs

• Current LED devices are fabricated
  by growing gallium nitride (GaN) on sapphire
  (Al2O3) or silicon carbide (SiC).
• Expensive in terms of /lumen
• Poor performance due to lattice mismatch 16 for
  GaN/Al2O3
• and 4 for GaN/SiC
• GaN/Al2O3 (90 of market) defect density 108-109
  cm-2
• Substrates are expensive and costly to process
• Small substrates 2/3rds of LEDs are grown on 2
  substrates
• Poor substrate reflectivity and thermal
  conductivity (Al2O3)

Threading dislocations due to lattice mismatch
Innovation ZrB2 Buffer Layer

• Growing a zirconium diboride (ZrB2) buffer layer
  enables the growth of high quality GaN on a
  relatively inexpensive Si substrate
• ZrB2 is lattice matched to GaN enabling high
  quality material
• Enables the replacement of a high cost substrate
  with a much lower substrate cost by 10x
• Three patents filed

Cost of Light Dollars per Lumen-Hour gt
(LampCost LaborCost)/LampLifetime)
EnergyUseEnergyCost LampLumens
OIDA Technology Roadmap
Nakamura, S, OIDA Solid-State Lighting
Workshop, Albuquerque, May 30, 2002 Merfeld,
DW, et al,J. of Electronic Materials, Vol 33, No.
11, 2004
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Silicon Substrate for LED Growth
Markets Lighting

• Incandescent
• Fluorescent
• Automotive
• Fixed mobile displays
• Medical sterilization,
• imaging, skin therapy
• Industrial curing
• Research instruments
• Detectors

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• a fabless design house developing patented SiFET
  technologies for ultra-high efficiency, low-power
  electronics

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The Problem
Low dropout regulators (LDOs) are used in almost
all portable electronics to ensure constant
supply voltage as the battery voltage falls with
time
The LDO chip itself uses some voltage of its
own(called the dropout voltage) The higher the
dropout voltage the lower the efficiency, and the
shorter the battery lifetime.Existing LDO chips
have dropout voltages gt50 mV and require
additional componentse.g. to ensure stable
operation
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Our Solution
Our patented Si-FET technology has several key
advantages

• ultra-low dropout voltages (lt20 mV) ? higher
  efficiency, longer battery lifetime
• requires fewer external components ? reduced
  volume, reduced cost, increased reliability
• Si-FET technology is robust and suitable for
  aerospace industry
• similar parts will be developed for the
  high-volume/low-margins commercial sector as well
  as the low-volume/high-margins aerospace industry

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The Opportunity
The LDO market is growing and is not dominated by
a single manufacturer
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The Company

• SJT Micropower Established in 2000 to protect IP
  being developed at ASU and demonstrate technical
  feasibility
• 3 international patents already issued and 3 more
  pending as a result of gt 1.5M in federally
  funded research at ASU
• Since 2005 we have been awarded 5 SBIR/STTR
  contracts from DARPA, NASA, SFAz and NIH totaling
  705k- 1.5M of Phase II funding is pending
• Si FET technology demonstrated at three
  commercial foundries and two government labs

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Summary Financials
Forecasted Revenue, Gross Margin Income
Product Revenue
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Our Team

• Steven Wood CEOgt 20 years experience in the
  power components industry.Has successfully led
  several businesses in the power electronics
  industry which have been acquired at attractive
  valuations.
• Trevor Thornton, PhD Founder and President of
  SJT Micropower.Currently professor of Electrical
  Engineering at ASU with 24 years experience
  designing and testing novel semiconductor devices
• Seth Wilk, PhD Senior Engineer ASU PhD 2005
  RF/Low noise circuit design
• William Lepkowski Senior Engineer PhD
  Candidate in EE, ASU MESFET layout and
  characterization
• Asha Balijepalli Principal RF Engineer PhD
  Candidate in EE, ASU. She has held engineering
  internship positions at Freescale where she has
  worked on LD-MOS power amplifier design.

Retained Osborne-Maledon as legal counselSeeking
CFO candidates
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Proposition
We are seeking 2.5M in funding over the next 18
months to develop prototypes in sufficient volume
to begin marketing in the US in Q3 2009.
Research
Development
Commercialization
Discovery
Technical
Integration
Prototype
Production
Feasibility
SJT Micropower SiFET technology
Full business plan and financials available on
request
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Overview of the Flexible Display Center at
Arizona State University
Nick Colaneri Flexible Display Center at Arizona
State University, Tempe, AZ 85287-0808, USA TEL
1-480-727-8971 e-mail nick.colaneri_at_asu.edu
http//flexdisplay.asu.edu
February 13, 2009
ASU Technology Forum
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FDC Dual Pathway
OBJECTIVE
Mission Speed the development and
commercialization of flexible displays
Provide Technology Demonstrators to show
capability to Army users
FFW SF-PDA
FFW, PEO Soldier, PM SWAR
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Strategic PartnershipGovernment-Industry-Academia
U.S. Army
Manufacturers Display Technology
Materials
Electronic Materials
Flexible Display Center
RD Labs Universities
Toolsets for Manufacturing
NC AT
System Integrators
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Innovation Capability Enabled byFacility, Tools,
Pilot Line Professional Staff
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EPD Technology Demonstrators
Effective Management of Plastic Substrate
Challenges Distortion and Defectivity
Effective Management of SS Substrate
Challenges Roughness and Stress
3.8-in. QVGA EPD on SS Zero-defectivity
3.8-in. QVGA EPD on PEN Worlds Highest
Temperature a-SiH directly fabricated on
polyester substrates
210 ppi EPD on SS High Pixel Density enables VGA
resolution at 3.8-in diagonal
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Conclusions

• FDC Effective Partnership Model and Powerful
  Capability enabling rapid advances in Flexible
  Display and Manufacturing Technology Development
• Enabling Commercial Successes towards
  Manufacturing
• High quality high performance plastic substrate
  DTF Planarised PEN
• Low temperature planarizing thin film material
  Honeywell PTS Materials Series
• Large Area mist coater EVG 150XL (GEN 3.5)
• Critical Path Technology Advances
• Materials, tools and processes for Flexible
  Substrate Systems
• State-of-the-art low temperature 180 C a-SiH
  TFT on flex technology
• Rugged / Conformal / Opaque ? Bendable / Rollable
  / Transparent transition underway (Plastic
  processing advances)