Task II Physical Design Tools

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Task II - Physical Design Tools
Current Task Participants Stanford Robert
Dutton, Simon Wong MIT Jacob White, Duane
Boning RPI Yannick Le Coz Overall
Objectives Develop a hierarchy of CAD tools to
support 1. the design and analysis of
electrical interconnects for above GHz
operations, 2. the synthesis and analysis of
system-on-a-chip with heterogeneous interconnect
technologies, and 3. variation analysis of
manufacturabiliity and performance limitations.

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Challenges

• Drastic increase in interconnect network
  complexity, material options and operating
  frequency.
• High-frequency effects (e.g., inductance, skin
  effect, ..) need to be accounted.
• Complex, long-range coupling effects (e.g.,
  substrate noise, ..) are difficult to model.
• Integration of alternative interconnect
  technologies (e.g., optical, RF, 3-D, ..)
  necessitates the analysis of heterogeneous
  interactions (electro-optical, electro-magnetic,
  electro-thermal, ..) and isolation.

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INTERCONNECT FOCUS RESEARCH CENTER
. .
. . 3-D Transmission Line Optical RF . .
Integration Analysis Synthesis
Network Processor
Application Pull
Technology Push
Physical Design Tools
Architecture Circuit
Mixed Signal
Collaborations with Design Center
. .
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High Frequency Behavior of InterconnectWhat are
the performance limits of on-chip interconnect ?

• Stanford University
• Faculty Simon Wong
• Students Richard Chang
• So Young Kim
• Frank OMahony
• Collaborators Robert Dutton, Stanford
• Jacon White, MIT
• Larry Pileggi, CMU

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Explore Wave Behavior of On-Chip
Interconnect (R-L-G-C instead of R-C)

• How will inductive effects affect signal
  integrity ?
• How should inductive effects of a complex chip be
  modeled ?
• What is the ultimate performance limit of an
  on-chip electrical interconnect (C / K1/2) ?
• What are the optimized interconnect structures
  that support the distribution of above GHz
  digital clock and data, and analog signals ?

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Low Loss Interconnect Structure

• Diminishing returns above 2 mm of ILD thickness
• Example 0.4 dB/mm loss _at_ 10 GHz, using 2 mm
  ILD, 10 mm wide wire

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Experimental Verification of Propagation Velocity

• Coplanar waveguide, 1 mm in length
• Propagation velocity approaches C/K1/2

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Effect of Loss on Standing Wave

• Wire loss causes skew
• Incident and reflected waves have mismatched
  amplitudes
• The residual travelling wave -- the difference
  between the incident and reflected wave
  amplitudes -- causes skew
• Use low-resistance, high-inductance wires to
  achieve low skew

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Low-Loss Differential Active Transmission Line

• Low loss reduces skew lt 1ps for 10 GHz clock
• Can be injection locked to external signal over a
  wide range (10 fo)

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Standing Wave Clock Network

• Use mutually injection-locked standing wave
  oscillators to form a grid
• Lock clock grid to external signal over a wide
  frequency range (10 fo)
• Tolerant to length mismatch between segments

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Normalized Power Spectral Density of Digital
Pulse dB
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Normalized Power Spectral Density of Modulated
Pulse dB
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Modulation System Implementation
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Circuit Schematic
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Interconnect Performance
RC Line with Similar Design Rules and Repeaters
LC Line with Modulation System
modulation

• 0.18 mm Process, 6-level Al interconnect
• Relaxed Rule 16 mm width, 1.9 mm ILD, 2 cm
  length
• 7.5 GHz LO delay of 278 ps (401 ps - 123 ps),
  speed 1/2 Cox power 14.2 mW

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Eye Diagram for 1GHz Signal Across 2cm
Interconnect

• Performance limited by rise time of input pulse

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Summary

• Simulate standing wave clock network with low
  skew.
• Demonstrate data propagation at 1/2 speed of
  light with optimized interconnect structure and
  modulation approach Demonstrate speed-power
  advantages over conventional repeater approach.

Future Directions

• Explore performance limits for data propagation
  near speed of light.
• Experimentally demonstrate standing wave clock
  network and verify performance.

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Floating Random-Walk Algorithms for Thermal and
Electromagnetic Analyses of Complex
IC-Interconnect Structures
(IFC Task 2 Physical Design Tools)

• Task Supervisor Prof. Y.L. Le Coz
• Research Associate Dr. R.B. Iverson
• Students K. Chatterjee (PhD '02, Intel Fellow)
• D. Krishna (MS '02)
• Industry Affiliates Dr. P. Bendix, Dr. W. Loh,
• Dr. D. Petranovic (LSI Logic)

Center for Integrated Electronics Rensselaer
Polytechnic Institute
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Electromagnetic Analysis Objectives and Approach
Objectives Create an efficient, parallelizable
random-walk (RW) algorithm for EM analysis of
complex, multilevel IC interconnects. Invent and
test a novel Dirichlet-Neumann (D-N) RW algorithm
for 1D TEM propagation. Formulate a 2D
generalization of the D-N RW algorithm.
Approach Use an unconventional infinite-domain
Greens function in developing RW field eqns.
Solve the Maxwell-Helmholtz eqn for vector and
scalar potentials.
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Results 1D Field Equations for D-N RWs (Forced)
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Results Heterogeneous Dielectric-Conductor,
Imaginary Part (unforced)
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Results Homogeneous Dielectric, Complex kf,
Imaginary Part (forced)
(See Poster for more details!)
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Thermal Analysis Objectives and Approach

• Objectives
• Develop an efficient random-walk (RW) methodology
  for thermal analysis of 3D IC transistor,
  inter-connect, and chip structures.
• Extend the thermal analysis metho-dology to
  include non-uniform heat generation (done)
  tightly stacked gdsII files (coded debugged).
• Support 3D integration projects in IFC Tasks V
  VI (MIT, RPI-SUNY Stanford).
• (See Poster for results!)

Approach Use random walks to stochastically solve
the 3D Poisson equation in global and local
domains.
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Summary Achievements for the Current Year (Y3)

• Invented A Dirichlet-Neumann (D-N) RW Algorithm
  for EM Analysis
• Verified solution of 1D TEM test problems (1)
  unforced, heterogeneous domain (2) forced,
  homogeneous domain.
• Developed mathematical theory for generalization
  of D-N RW field eqns to homogeneous, 2D domains
  (Bessel functions).
• Continued Thermal-Analysis Collaboration
• Previously reported collaborations Y1, Stanford
  (Wong) Y2, MIT(Reif).
• Emphasis this year, Y3 RPI shift-register array
  (McDonald, Cale).
• Developed applied capability for inhomogeneous
  power dissipation.
• Coded debugged tightly stacked gdsII file
  capability.
• New Initiative Begun Interconnect h-Moment
  Extraction using RWs
• Presently, RC in the future, RLC RLCM delay
  crosstalk analysis.
• Novel Feynman diagrammatic H(s) perturbation
  expansion RW evaluation.
• Promises a future full-parallel software or
  hardware implementation for high-speed,
  brute-force timing verification.
• Obtained addnl support from LSI Logic for Y4Y6.

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Proposed Future Plan (Y4)

• Continue EM Thermal Algorithm Development
• Numerically verify 2D D-N RW eqns for
  Maxwell-Helmholtz soln in materially
  homogeneous domains.
• Create a new D-N RW algorithm for the materially
  heterogeneous heat eqn, subject to pure Dirichlet
  BCs. (Try to improve the current RW thermal
  approach.)
• Collaborate with MIT, RPI, and/or Stanford, as
  appropriate.
• New Initiative h-Extraction RW Algorithm
• Develop the Feynman diagrammatic formalism.
• Code an RC h-extraction test algorithm for proof
  of concept.
• Test RW algorithm against SPICE for m0, m1 m2
  moments.

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Impact of Process Variations on Emerging
Interconnect Technologies Prof. Duane Boning
(MIT)Students Nigel Drego, Allan Lum, Vikas
Mehrotra, Mike Mills Collaborations A.
Chandrakasan, L. Kimerling, C. Fonstad
graduated
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1. Variation Impact on Interconnect Clock Skew
and Signal Delay in Deeply Scaled Interconnect
A. Clock Skew Variation Impact Analysis
Projections

• Interconnect variations e.g. metal thickness due
  to copper CMP
• Device variations
• 2 buffers 1 latch in each path
• Monte carlo simulations on device params
• Case 1 3s limits for Leff, tox, VDD
• Case 2 3s limits for tox, VDD assume 50
  model-based corrections in Leff
• Calculate total 3s skew including all device
  stages

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Clock Skew Variation Impact Analysis Projections
interconnect variation smallimpact
device variationincreasing skew
models ofsystematic variation reduceskew
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B. Impact of Variation on Signal Path Delays

• Calculate max interconnect length (Lmax) and
  optimal buffers (bufopt) for various pitch and
  technology generations such that global clock
  frequency constraints (ffc) are met.
• Insert repeaters to minimize delay
• Calculate first order delay
• By 50nm generation, Lmax in global tier is
  lt2Lchip, even for 3X pitch
• Variation in devices and wires along paths
  degrades Lmax

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2. On-Chip Optical Receiver Circuits

• "Conventional" (telecommunications driven)
  on-chip optical I/O signal reception demands
  speed but skew and clocking not big issues. In
  contrast
• On-chip optical clock distribution
• clock skew across multiple receivers is critical
• relatively small number of receivers (e.g. 16,
  64) so less demanding on receiver size and power
• On-chip optical signaling
• receiver size and power must be low to support
  significant numbers of signal paths on the chip
• speed, latency, and robustness are key

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Variation in Optical Clock Distribution

• Approach
• off-chip optical source
• distribute by waveguides
• optoelectronic conversion detector and
  receiver circuit
• local electrical clock network
• Potential Advantages
• low skew distribution high speed clocking
• low noise
• power reduction
• Variation Concern
• how will variation introduce skew and limit
  optical clocks?

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Second Generation Optical Clock Receiver Circuit
Design
Student Allan Lum

• Design complete
• 1 GHz with 100 fF photodiode capacitance(100 MHz
  with 1 pF photodiode capacitance)
• Power 19.3 mW (steady state)
• Size 205 mm x 170 mm
• Variation analysis

• Process variation remains a key challenge to
  achieving desired clock speed

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On-Chip Optical Data Receiver
Two Types of Transmission
Student Mike Mills
Clock
Data Bits

• No knowledge of phase
• Concerned only with skew, not latency
• Circuit often much larger in area

• Already have clock signal
• Latency is key issue
• Need small area to replicate in large numbers (64
  bit bus)

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On-Chip Optical Data Receiver Sense-Amp Approach

• Small input signals must be amplified to
  rail-to-rail outputs
• As in memories, we can use a sense amplifier
• New problem photodiodes have very high
  capacitance
• isolate using a current mirror
• Adding current mirrors significantly increases
  maximum speed

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On-Chip Optical Data Receiver Simulation Results

• Adding current mirrors significantly increases
  maximum speed
• Benefits are larger when Cdiode is bigger
• Matching is a bigger issue in current mirror
  approach
• Next steps
• Detailed variation analysis
• Chip fabrication and testing

Approximate maximum speeds as simulated in HSpice
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3. Variation in Low Power Interconnect
Low-Swing Signaling

• Interconnects consume a significant fraction of
  total power in current chips
• Approach Low-swing signaling for power
  reduction
• Reduce voltage swing on busses to reduce power
• Low-swing drivers with full-swing recovery
  receivers
• Key question A viable technique in future
  low-power systems?
• Performance vs. power tradeoffs
• Cross-talk and noise susceptibility
• Timing dependencies variation has larger impact
  in low-swing signaling
• Future Work Examine challenges/viability of
  future low-swing signaling approaches from a
  variation perspective

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Low-Swing Signaling Alternatives
Common Level Converter

• Consider existing and new low-swing signaling
  approaches for
• Potential power savings
• Complexity and area tradeoffs
• Cross-talk susceptibility
• Sensitivity to variation
• Design and fabricate test circuits to evaluate
  low-swing reception errors as
• voltage scales lower
• interconnect length and CL increases
• feature size/pitch decreases

Differential Circuit
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Summary Variation Impact and Alternative
Technology Evaluation

• Understanding of variation and its impact in
  interconnect systems is crucial to understand
• Limits of performance, yield, and reliability
• The viability of alternative technologies
• Projects
• Variation impact on interconnect clock skew and
  signal delay in deeply scaled interconnect
  (completed - Mehrotra PhD 6/2001)
• On chip optical receivers variation robust
  design
• a. Clock receiver (design complete - Lum SM
  8/2001)
• b. Data receiver circuit (in progress - Mills)
• c. Fabrication/demonstration (planned - Mills,
  Drego, Fonstad)
• Variation in low power interconnect low-swing
  signaling (planned)