Chapter 2. Machine Instructions and Programs

1
Chapter 2. Machine Instructions and Programs

• CENG 2213
• Computer Organization
• Instructor Dr. Shen

2
Objectives

• Machine instructions and program execution,
  including branching and subroutine call and
  return operations.
• Number representation and addition/subtraction in
  the 2s-complement system.
• Addressing methods for accessing register and
  memory operands.
• Assembly language for representing machine
  instructions, data, and programs.
• Program-controlled Input/Output operations.
• Operations on stack, queue, list, linked-list,
  and array data structures.

3
Number, Arithmetic Operations, and Characters
4
Unsigned Integer

• Consider a n-bit vector of the form
• where ai0 or 1 for i in 0, n-1.
• This vector can represent positive integer values
  V A in the range 0 to 2n-1, where

5
Signed Integer

• 3 major representations
• Sign and magnitude
• Ones complement
• Twos complement
• Assumptions
• 4-bit machine word
• 16 different values can be represented
• Roughly half are positive, half are
  negative

6
Sign and Magnitude Representation
High order bit is sign 0 positive (or zero), 1
negative Three low order bits is the magnitude
0 (000) thru 7 (111) Number range for n bits
/-2n-1 -1 Two representations for 0
7
Ones Complement Representation

• Subtraction implemented by addition 1's
  complement
• Still two representations of 0! This causes some
  problems
• Some complexities in addition

8
Twos Complement Representation
like 1's comp except shifted one
position clockwise

• Only one representation for 0
• One more negative number than positive number

9
Binary, Signed-Integer Representations
B
V
alues represented
Page 28
Sign and
b
b
b
b
magnitude
1'
s complement
2'
s complement
3
2
1
0
7

7

7

0
1
1
1
6

6

6

0
1
1
0
5

5

5

0
1
0
1
4

4

4

0
1
0
0
3

3

3

0
0
1
1
2

2

2

0
0
1
0
1

1

1

0
0
0
1
0

0

0

0
0
0
0
8
-
0
-
7
-
1
0
0
0
1
-
6
-
7
-
1
0
0
1
2
-
5
-
6
-
1
0
1
0
3
-
4
-
5
-
1
0
1
1
4
-
3
-
4
-
1
1
0
0
5
-
2
-
3
-
1
1
0
1
6
-
1
-
2
-
1
1
1
0
7
-
0
-
1
-
1
1
1
1
Figure 2.1. Binary, signed-integer
representations.
10
Comparison

• Sign and Magnitude
• Cumbersome addition/subtraction
• Must compare magnitudes to determine sign of
  result
• Ones Complement
• Simply bit-wise complement
• Twos Complement
• Simply bit-wise complement 1

11
Addition of Positive Numbers
1
0
0
1
1

1

0

0

0
1
1
0
1
Carry-out
Figure 2.2. Addition of 1-bit numbers.
12
Addition and Subtraction Sign Magnitude
4 3 7
0100 0011 0111
-4 (-3) -7
1100 1011 1111
result sign bit is the same as the operands' sign
when signs differ, operation is subtract, sign of
result depends on sign of number with the larger
magnitude
4 - 3 1
0100 1011 0001
-4 3 -1
1100 0011 1001
13
Addition and Subtraction 1s Complement
4 3 7
0100 0011 0111
-4 (-3) -7
1011 1100 10111 1 1000
End around carry
4 - 3 1
0100 1100 10000 1 0001
-4 3 -1
1011 0011 1110
End around carry
14
Addition and Subtraction 1s Complement
Why does end-around carry work? Its
equivalent to subtracting 2 and adding 1
n
n
n
M - N M N M (2 - 1 - N) (M - N)
2 - 1
(M gt N)
n
n
-M (-N) M N (2 - M - 1) (2 - N
- 1) 2 2
- 1 - (M N) - 1
n-1
M N lt 2
n
n
after end around carry
n
2 - 1 - (M N)
this is the correct form for representing -(M
N) in 1's comp!
15
Addition and Subtraction 2s Complement
4 3 7
0100 0011 0111
-4 (-3) -7
1100 1101 11001
If carry-in to the high order bit carry-out
then ignore carry if carry-in differs
from carry-out then overflow
4 - 3 1
0100 1101 10001
-4 3 -1
1100 0011 1111
Simpler addition scheme makes twos complement the
most common choice for integer number systems
within digital systems
16
Addition and Subtraction 2s Complement
Why can the carry-out be ignored?
-M N when N gt M
n
n
M N (2 - M) N 2 (N - M)
n
Ignoring carry-out is just like subtracting 2
n-1
-M -N where N M lt 2
n
n
-M (-N) M N (2 - M) (2 - N)
2 - (M N) 2
n
n
After ignoring the carry, this is just the right
twos complement representation for -(M N)!
17
2s-Complement Add and Subtract Operations
Page 31
Figure 2.4. 2's-complement Add and Subtract
operations.
18
Overflow - Add two positive numbers to get a
negative number or two negative numbers to get a
positive number
-1
-1
0
0
-2
-2
1111
0000
1
1111
0000
1
1110
1110
0001
0001
-3
-3
2
2
1101
1101
0010
0010
-4
-4
1100
3
1100
3
0011
0011
-5
-5
1011
1011
0100
4
0100
4
1010
1010
-6
-6
0101
0101
5
5
1001
1001
0110
0110
-7
-7
6
6
1000
0111
1000
0111
-8
-8
7
7
-7 - 2 7
5 3 -8
19
Overflow Conditions
0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 0
1 0 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1
5 3 -8
-7 -2 7
Overflow
Overflow
0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1
1 1 1 1 1 1 0 1 1 0 1 1 1 1 0 0 0
5 2 7
-3 -5 -8
No overflow
No overflow
Overflow when carry-in to the high-order bit does
not equal carry out
20
Sign Extension

• Task
• Given w-bit signed integer x
• Convert it to wk-bit integer with same value
• Rule
• Make k copies of sign bit
• X ? xw1 ,, xw1 , xw1 , xw2 ,, x0

w
k copies of MSB
w
k
21
Sign Extension Example
short int x 15213 int ix (int) x
short int y -15213 int iy (int) y
22
Memory Locations, Addresses, and Operations
23
Memory Location, Addresses, and Operation

• Memory consists of many millions of storage
  cells, each of which can store 1 bit.
• Data is usually accessed in n-bit groups. n is
  called word length.

24
Memory Location, Addresses, and Operation

• 32-bit word length example

32 bits

b
b
b
b
31
30
1
0
for positive numbers
Sign bit
b
0

31
for negative numbers
b
1

31
(a) A signed integer
8 bits
8 bits
8 bits
8 bits
ASCII
ASCII
ASCII
ASCII
character
character
character
character
(b) Four characters
25
Memory Location, Addresses, and Operation

• To retrieve information from memory, either for
  one word or one byte (8-bit), addresses for each
  location are needed.
• A k-bit address memory has 2k memory locations,
  namely 0 2k-1, called memory space.
• 24-bit memory 224 16,777,216 16M (1M220)
• 32-bit memory 232 4G (1G230)
• 1K(kilo)210
• 1T(tera)240

26
Memory Location, Addresses, and Operation

• It is impractical to assign distinct addresses to
  individual bit locations in the memory.
• The most practical assignment is to have
  successive addresses refer to successive byte
  locations in the memory byte-addressable
  memory.
• Byte locations have addresses 0, 1, 2, If word
  length is 32 bits, they successive words are
  located at addresses 0, 4, 8,

27
Big-Endian and Little-Endian Assignments
Big-Endian lower byte addresses are used for the
most significant bytes of the word Little-Endian
opposite ordering. lower byte addresses are used
for the less significant bytes of the word
W
ord
address
Byte address
Byte address
0
1
2
3
0
0
3
2
1
0
4
5
6
7
4
7
6
5
4
4


k
k
k
k
k
k
k
k
k
k
2
4
-
2
3
-
2
2
-
2
1
-
2
4
-
2
4
-
2
1
-
2
2
-
2
3
-
2
4
-
(a) Big-endian assignment
(b) Little-endian assignment
Figure 2.7. Byte and word addressing.
28
Memory Location, Addresses, and Operation

• Address ordering of bytes
• Word alignment
• Words are said to be aligned in memory if they
  begin at a byte addr. that is a multiple of the
  num of bytes in a word.
• 16-bit word word addresses 0, 2, 4,.
• 32-bit word word addresses 0, 4, 8,.
• 64-bit word word addresses 0, 8,16,.
• Access numbers, characters, and character strings

29
Memory Operation

• Load (or Read or Fetch)
• Copy the content. The memory content doesnt
  change.
• Address Load
• Registers can be used
• Store (or Write)
• Overwrite the content in memory
• Address and Data Store
• Registers can be used

30
Instruction and Instruction Sequencing
31
Must-Perform Operations

• Data transfers between the memory and the
  processor registers
• Arithmetic and logic operations on data
• Program sequencing and control
• I/O transfers

32
Register Transfer Notation

• Identify a location by a symbolic name standing
  for its hardware binary address (LOC, R0,)
• Contents of a location are denoted by placing
  square brackets around the name of the location
  (R1?LOC, R3 ?R1R2)
• Register Transfer Notation (RTN)

33
Assembly Language Notation

• Represent machine instructions and programs.
• Move LOC, R1 R1?LOC
• Add R1, R2, R3 R3 ?R1R2

34
Basic Instruction Types

• High-level language C A B
• Action C ? A B
• Assembly Add A, B, C
• Three-address instruction Operation Source1,
  Source2, Destination
• Two-address instructionOperation Source,
  Destination
• Add A, B B ?A B

35
Basic Instruction Types

• Need to add something to the above two-address
  instruction to finishMove B, C C ? B
• One-address instruction (to fit in one word
  length)
• Accumulator Add A
• Load A
• Add B
• Store C
• Zero-address instructions (stack operation)

36
Using Registers

• Registers are faster
• Shorter instructions
• The number of registers is smaller (e.g. 32
  registers need 5 bits)
• Potential speedup
• Minimize the frequency with which data is moved
  back and forth between the memory and processor
  registers.

37
Using Registers

• Load A, Ri
• Store Ri, A
• Add A, Ri
• Add Ri, Rj
• Add Ri, Rj, Rk
• Move Source, Destination
• Move A, Ri Load A, Ri
• Move Ri, A Store Ri, A

38
Using Registers

• CAB
• In the processors where arithmetic operations are
  allowed only on operands in registerMove A,
  RiMove B, RjAdd Ri, RjMove Rj, C
• In the processors where one operand may be in the
  memory but the other one must be in
  registersMove A, RiAdd B, RiMove Ri, C

39
Instruction Execution and Straight-Line Sequencing
Contents
Address
Assumptions - One memory operand per
instruction - 32-bit word length - Memory is
byte addressable - Full memory address can be
directly specified in a single-word instruction
i
A,R0
Begin execution here
Move
3-instruction
program
i
4
B,R0
Add
segment
i
8
R0,C
Move
A
Data for
B
the program

• Two-phase procedure
• Instruction fetch
• Instruction execute

C
Page 43
Figure 2.8. A program for C A B.
40
Branching
NUM1,R0
Move
i
i
4

NUM2,R0
Add
i
8

NUM3,R0
Add

NUM
n
,R0
Add
i
4
n
4
-

i
4
n
R0,SUM
Move


SUM
NUM1
NUM2

NUM
n
Figure 2.9. A straight-line program for adding
n numbers.
41
Branching
N,R1
Move
R0
Clear
LOOP
Determine address of
"Next" number and add
"Next" number to R0
Program
loop
R1
Decrement
LOOP
Branchgt0
Branch target
R0,SUM
Move
Conditional branch

SUM
N
n
NUM1
NUM2
Figure 2.10. Using a loop to add n numbers.

NUM
n
42
Condition Codes

• Condition code flags
• Condition code register / status register
• N (negative)
• Z (zero)
• V (overflow)
• C (carry)
• Different instructions affect different flags

43
Generating Memory Addresses

• How to specify the address of branch target?
• Can we give the memory operand address directly
  in a single Add instruction in the loop?
• Use a register to hold the address of NUM1 then
  increment by 4 on each pass through the loop.

44
Addressing Modes
45
Addressing Modes
Name
Assem
bler
syn
tax
Addressing
function

• The different ways in which the location of an
  operand is specified in an instruction are
  referred to as addressing modes.

Immediate
V
alue
Op
erand

V
alue
Register
R
i
EA

R
i
Absolute
(Direct)
LOC
EA

LOC
Indirect
(R
i
)
EA

R
i

(LOC)
EA

LOC
Index
X(R
i
)
EA

R
i


X
Base
with
index
(R
i
,R
j
)
EA

R
i


R
j

Base
with
index
X(R
i
,R
j
)
EA

R
i


R
j


X
and
offset
Relative
X(PC)
EA

PC

X
Autoincremen
t
(R
i
)
EA

R
i


Incremen
t
R
i
?
Autodecrement
(R
i
)
Decremen
t
R
i

EA

R
i

46
Implementation of Variables

• A variable is represented by allocating a
  register or a memory location to hold its value.
• Register mode
• Absolute mode
• Move LOC, R2

47
Implementation of Constants

• Immediate mode
• Move 200immediate, R0
• Move 200, R0
• A B 6
• Move B, R1
• Add 6, R1
• Move R1, A

48
Indirection and Pointers

• Indirect mode the effective address (EA) of the
  operand is the contents of a register or memory
  location whose address appears in the instruction.

Add (R1),R0
Add (A),R0
Main
memory
A
B
Operand
B
Register
Operand
R1
B
B
(a) Through a general-purpose register
(b) Through a memory location
Figure 2.11. Indirect addressing.
49
Indirection and Pointers

• (a)
• R1 has B2000, 5 is stored in MEM 2000
• Add (R1), R0 Add 2000, R0 5R0?R0
• (b)
• A1000, B2000, 2000 is stored in MEM 1000
• Add (A), R0 Add(1000), R0 Add 2000, R0
  5R0?R0
• Add 1000, R0 ?

2000R0?R0
50
Indirection and Pointers
The register or memory location that contains the
address of an operand is called a pointer.
Contents
Address
Move
N,R1
Initialization
Move
NUM1,R2
Clear
R0
Add
LOOP
(R2),R0
Add
4,R2
Decrement
R1
LOOP
Branchgt0
Move
R0,SUM
Figure 2.12. Use of indirect addressing in the
program of Figure 2.10.
51
Indirection and Pointers

• C-language A B
• Move B, R1Move (R1), A
• Indirect addressing Move (B), A
• Indirect addressing through memory
• Indirect addressing through registers

52
Indexing and Arrays

• Index mode the effective address of the operand
  is generated by adding a constant value to the
  contents of a register.
• Index register
• X(Ri) EA X Ri
• The constant X may be given either as an explicit
  number or as a symbolic name representing a
  numerical value.
• If X is shorter than a word, sign-extension is
  needed.

53
Indexed Addressing
Add 20(R1),R2
R1
1000
1000
20 offset
Operand
1020
(a) Offset is given as a constant
Add 1000(R1),R2
R1
20
1000
20 offset
Operand
1020
(b) Offset is in the index register
Figure 2.13. Indexed addressing.
54
Example Student Record List
n
N
Student ID
LIST
Test 1
LIST 4
Student 1
Test 2
LIST 8
Test 3
LIST 12
Student ID
LIST 16
Test 1
Student 2
Test 2
Test 3

Figure 2.14. A list of students' marks.
55
Example (Cont)

• Compute the sum of all scores obtained on each of
  the tests and store these three sums in memory
  locations SUM1, SUM2, and SUM3.

Move LIST,R0
Clear
R1
Clear
R2
Clear
R3
Move
N,R4
Add
4(R0),R1
LOOP
R0 doesnt change
Add
8(R0),R2
A
d
d
12(R0),R3
Add
16,R0
Decrement
R4
LOOP
Branchgt0
Move
R1,SUM1
R2,SUM2
Move
Move
R3,SUM3
56
Indexing and Arrays

• In general, the Index mode facilitates access to
  an operand whose location is defined relative to
  a reference point within the data structure in
  which the operand appears.
• Several variations(Ri, Rj) EA Ri
  RjX(Ri, Rj) EA X Ri Rj

57
Relative Addressing

• Relative mode the effective address is
  determined by the Index mode using the program
  counter in place of the general-purpose register.
• X(PC) note that X is a signed number
• Branchgt0 LOOP
• This location is computed by specifying it as an
  offset from the current value of PC.
• Branch target may be either before or after the
  branch instruction, the offset is given as a
  singed num.

58
Additional Modes

• Autoincrement mode the effective address of the
  operand is the contents of a register specified
  in the instruction. After accessing the operand,
  the contents of this register are automatically
  incremented to point to the next item in a list.
• (Ri). The increment is 1 for byte-sized
  operands, 2 for 16-bit operands, and 4 for 32-bit
  operands.
• Autodecrement mode -(Ri) decrement first

N,R1
Move
Initialization
NUM1,R2
Move
R0
Clear
(R2),R0
LOOP
Add
R1
Decrement
LOOP
Branchgt0
R0,SUM
Move
Figure 2.16. The Autoincrement addressing mode
used in the program of Figure 2.12.
59
Assembly Language
60
Assembly Language

• Machine instructions are represented by 0s and
  1s cool but
• Symbolic names Move, Add, Increment, Branch,
• Mnemonics MOV, ADD, INC, BRA,
• A complete set of such symbolic names and rules
  for their use constitute an assembly language.
• The set of rules for using the mnemonics is
  called the syntax of the language.
• Assembler
• Source program object program

61
Assembly language

• May or may not be case sensitivity
• Op code binary pattern for the operation
• Several exampleADD 5, R3ADDI 5, R3MOVE 5,
  (R2)MOVEI 5, (R2)

62
Assembler Directives

• Allow programmer to specify other information
  needed to translate the source program into
  object program assembler directives/commands.
• SUM EQU 20 / LOCA EQU 1000
• Label Operation Operand(s) Comment

63
Sample Program
100
N,R1
Move
104
NUM1,R2
Move
R0
Clear
108
(R2),R0
112
LOOP
Add
Assembler has to know
- How to interpret the names - Where to place the
instructions in the memory - Where to place the
data operands in the memory
4,R2
116
Add
R1
120
Decrement
124
LOOP
Branchgt0
R0,SUM
128
Move
132
200
SUM
100
204
N
NUM1
208
NUM2
212
NUM
n
604
Figure 2.17. Memory arrangement for the program
in Figure 2.12.
64
Sample Program
Memory
Addressing
address
or
data
lab
el
Op
eration
information
Assem
bler
directiv
es
SUM
EQU
200
ORIGIN
204
N
D
A
T
A
W
ORD
100
NUM1
RESER
VE
400
ORIGIN
100
Statemen
ts
that
ST
AR
T
MO
VE
N,R1
generate
MO
VE
NUM1,R2
mac
hine
CLR
R0
instructions
LOOP
ADD
(R2),R0
ADD
4,R2
DEC
R1
BGTZ
LOOP
MO
VE
R0,SUM
Assem
bler
directiv
es
RETURN
END
ST
AR
T
65
Assembly and Execution of Programs

• Assemblers task (source ? object)
• Replace all symbols denoting operations and
  addressing modes with the binary codes used in
  machine instructions
• Replace all names and labels with their actual
  values
• Assign addresses to instructions and data blocks
  (ORIGIN, DATAWORD, RESERVE)
• Determine the values that replace the names (EQU,
  label)
• Branch address (Relative addressing, branch
  offset)
• Scan through the source program, keep track of
  all names and the numerical values that
  correspond them in a symbol table.
• What if a name appears as an operand before it is
  given a value (forward branch)?
• Two-pass assembler

66
Assembly and Execution of Programs

• Loader load the object program from the disk
  into memory
• Already be in memory
• Know the length of the program and the address in
  the memory where it will be stored
• Branch to the first instruction to be executed
• Debugger let user find errors easily
• Number notation decimal, binary (),
  hexadecimal/hex ()

67
Basic Input/Output Operations
68
I/O

• The data on which the instructions operate are
  not necessarily already stored in memory.
• Data need to be transferred between processor and
  outside world (disk, keyboard, etc.)
• I/O operations are essential, the way they are
  performed can have a significant effect on the
  performance of the computer.

69
Program-Controlled I/O Example

• Read in character input from a keyboard and
  produce character output on a display screen.
• Rate of data transfer (keyboard, display,
  processor)
• Difference in speed between processor and I/O
  device creates the need for mechanisms to
  synchronize the transfer of data.
• A solution on output, the processor sends the
  first character and then waits for a signal from
  the display that the character has been received.
  It then sends the second character. Input is sent
  from the keyboard in a similar way.

70
Program-Controlled I/O Example

• - Registers
• Flags
• - Device interface

71
Program-Controlled I/O Example

• Machine instructions that can check the state of
  the status flags and transfer dataREADWAIT
  Branch to READWAIT if SIN 0
  Input from DATAIN to R1WRITEWAIT Branch to
  WRITEWAIT if SOUT 0
  Output from R1 to DATAOUT

72
Program-Controlled I/O Example

• Memory-Mapped I/O some memory address values
  are used to refer to peripheral device buffer
  registers. No special instructions are needed.
  Also use device status registers.READWAIT
  Testbit 3, INSTATUS
  Branch0 READWAIT MoveByte
  DATAIN, R1

73
Program-Controlled I/O Example
Mo
v
e
LOC,R0
Initialize
p
oin
ter
register
R0
to
p
oin
t
to
the
address
of
the
first
lo
cation
in
memory
where
the
c
haracters
are
to
b
e
stored.
READ
T
estBit
3,INST
A
TUS
W
ait
for
a
c
haracter
to
b
e
en
tered
Branc
h0
READ
in
the
k
eyb
oard
buffer
D
A
T
AIN.
Mo
v
eByte
D
A
T
AIN,(R0)
T
ransfer
the
c
haracter
from
D
A
T
AIN
in
to
the
memory
(this
clears
SIN
to
0).
ECHO
T
estBit
3,OUTST
A
TUS
W
ait
for
the
displa
y
to
b
ecome
ready
.
Branc
h0
ECHO
Mo
v
eByte
(R0),D
A
T
A
OUT
Mo
v
e
the
c
haracter
just
read
to
the
displa
y
buffer
register
(this
clears
SOUT
to
0).
Compare
CR,(R0)
Chec
k
if
the
c
haracter
just
read
is
CR
(carriage
return).
If
it
is
not
CR,
then
Branc
h
?0
READ
branc
h
bac
k
and
read
another
c
haracter.
Also,
incremen
t
the
p
oin
ter
to
store
the
next
c
haracter.
Figure 2.20. A program that reads a line of
characters and displays it.
74
Program-Controlled I/O Example

• Assumption the initial state of SIN is 0 and
  the initial state of SOUT is 1.
• Any drawback of this mechanism in terms of
  efficiency?
• Two wait loops?processor execution time is wasted
• Alternate solution?
• Interrupt

75
Stacks and Queues
76
Stacks

• A list of data elements, usually words or bytes,
  with the accessing restriction that elements can
  be added or removed at one end of the list only.
• Top / Bottom / Pushdown Stack
• Last-In-First-Out (LIFO)
• Push / Pop

77
Stacks
0

Stack
pointer
register
Current
SP
28
-
top element
17
739
Stack

Bottom
BOTTOM
43
element

k
2
1
-
Figure 2.21. A stack of words in the memory.
78
Stacks

• Stack Pointer (SP)
• Push
• Subtract 4, SPMove NEWITEM, (SP)Move
  NEWITEM, -(SP)
• Pop
• Move (SP), ITEMAdd 4, SPMove (SP), ITEM

79
Stacks
0

SP
19
28
-
28
-
17
SP
17
SP
28
-
739
739
17
Stack
739



43
43
43

ITEM
NEWITEM
19
28
-
k
2
1
-
(b) After pop into ITEM
(a) After push from NEWITEM
Figure 2.22. Effect of stack operations on the
stack in Figure 2.21.
80
Stacks

• The size of stack in a program is fixed in
  memory.
• Need to avoid pushing if the maximum size is
  reached
• Need to avoid popping if stack is empty
• Compare instruction Compare src, dstdst
  srcWill not change the values of src and dst.

81
Stacks
SAFEPOP
Compare
2000,SP
Chec
k
to
see
if
the
stac
k
p
oin
ter
con
tains
Branc
h
gt
0
EMPTYERR
OR
an
address
v
alue
greater
than
2000.
If
it
do
es,
the
stac
k
is
empt
y
.
Branc
h
to
the
routine
EMPTYERR
OR
for
appropriate
action.
Mo
v
e
(SP),ITEM
Otherwise,
p
op
the
top
of
the
stac
k
in
to
memory
lo
cation
ITEM.
(a) Routine for a safe pop operation
SAFEPUSH
Compare
1500,SP
Chec
k
to
see
if
the
stac
k
p
oin
ter
?
Branc
h
0
FULLERR
OR
con
tains
an
address
v
alue
equal
to
or
less
than
1500.
If
it
do
es,
the
stac
k
is
full.
Branc
h
to
the
routine
FULLERR
OR
for
appropriate
action.

Mo
v
e
NEWITEM,
(SP)
Otherwise,
push
the
elemen
t
in
memory
lo
cation
NEWITEM
on
to
the
stac
k.
(b) Routine for a safe push operation
Figure 2.23. Checking for empty and full errors
in pop and push operations.
82
Queues

• Data are stored in and retrieved from a queue on
  a First-In-First-Out (FIFO) basis.
• New data are added at the back (high-address end)
  and retrieved from the front (low-address end).
• How many pointers are needed for stack and queue,
  respectively?
• Circular buffer

1, 2
83
Subroutines
84
Subroutines

• It is often necessary to perform a particular
  subtask (subroutine) many times on different data
  values.
• To save space, only one copy of the instructions
  that constitute the subroutine is placed in the
  memory.
• Any program that requires the use of the
  subroutine simply branches to its starting
  location (Call).
• After a subroutine has been executed, it is said
  to return to the program that called the
  subroutine, and the program resumes execution.
  (Return)

Memory
Memory
location
Calling program
location
Subroutine SUB
1000
200
Call SUB
first instruction
204
next instruction
Return
85
Subroutines

• Since the subroutine may be called from different
  places in a calling program, provision must be
  made for returning to the appropriate location.
• Subroutine Linkage method use link register to
  store the PC.
• Call instruction
• Store the contents of the PC in the link register
• Branch to the target address specified by the
  instruction
• Return instruction
• Branch to the address contained in the link
  register

86
Subroutines
Memory
Memory
location
Calling program
location
Subroutine SUB
1000
200
Call SUB
first instruction
204
next instruction
Return
1000
204
PC
204
Link
Return
Call
Figure 2.24. Subroutine linkage using a link
register.
87
Subroutine Nesting and The Processor Stack

• If a subroutine calls another subroutine, the
  contents in the link register will be destroyed.
• If subroutine A calls B, B calls C, after C has
  been executed, the PC should return to B, then A
• LIFO Stack
• Automatic process
• by the Call instruction
• Processor stack

MEM location of B
SP?
MEM location of A
88
Parameter Passing

• Exchange of information between a calling program
  and a subroutine.
• Several ways
• Through registers
• Through memory locations
• Through stack

89
Passing Parameters through Processor Registers
Calling
program
Mo
v
e
N,R1
R1
serv
es
as
a
coun
ter.
Mo
v
e
NUM1,R2
R2
p
oints
to
the
list.
Call
LIST
ADD
Call
subroutine.
Mo
v
e
R0,SUM
Sa
v
e
result.
.
.
.
Subroutine
LIST
ADD
Clear
R0
Initialize
sum
to
0.
LOOP
Add
(R2),R0
Add
en
try
from
list.
Decremen
t
R1
Branc
h
LOOP
gt
0
Return
Return
to
calling
program.
Figure 2.25. Program of Figure 2.16 written as a
subroutine parameters passed through registers.
90
Passing Parameters through Stack
- Passing by reference - Passing by value
Assume
top
of
stac
k
is
at
lev
el
1
b
elo
w.

Mo
v
e
NUM1,
(SP)
Push
parameters
on
to
stac
k.

Mo
v
e
N,
(SP)
Call
LIST
ADD
Call
subroutine
(top
of
stac
k
at
lev
el
2).
Mo
v
e
4(SP),SUM
Sa
v
e
result.
Add
8,SP
Restore
top
of
stac
k
(top
of
stac
k
at
lev
el
1).
?
R2
Lev
el
3
.
.
.
R1
R0


LIST
ADD
Mo
v
eMultiple
R0
R2,
(SP)
Sa
v
e
registers
?
(top
of
stac
k
at
lev
el
3).
Return
address
Lev
el
2
Mo
v
e
16(SP),R1
Initialize
coun
ter
to
n
.
n
Mo
v
e
20(SP),R2
Initialize
p
oin
ter
to
the
list.
NUM1
Clear
R0
Initialize
sum
to
0.
?
LOOP
Add
(R2),R0
Add
en
try
from
list.
Lev
el
1
Decremen
t
R1
Branc
h
gt
0
LOOP
Mo
v
e
R0,20(SP)
Put
result
on
the
stac
k.

(b) Top of stack at various times
Mo
v
eMultiple
(SP),R0
R2
Restore
registers.
Return
Return
to
calling
program.
Figure 2.26. Program of Figure 2.16 written as a
subroutine parameters passed on the stack.
(a) Calling program and subroutine
Page 76
91
The Stack Frame

• Some stack locations constitute a private work
  space for a subroutine, created at the time the
  subroutine is entered and freed up when the
  subroutine returns control to the calling
  program. Such space is called a stack frame.
• Frame pointer (FP)
• Index addressing to access data inside
  frame-4(FP), 8(FP),

92
Additional Instructions
93
Logic Instructions

• AND
• OR
• NOT (whats the purpose of the following)Not
  R0Add 1, R0
• Determine if the leftmost character of the four
  ASCII characters stored in the 32-bit register R0
  is Z (01011010)And FF000000, R0Compare
  5A000000, R0Branch0 YES

94
Logical Shifts

• Logical shift shifting left (LShiftL) and
  shifting right (LShiftR)

C
R0
0
.
.
.
before
0
0
0
0
1
1
1
1
1
.
.
.
after
1
1
1
0
0
0
1
0
1
(a) Logical shift left
LShiftL 2,R0
C
R0
0
.
.
.
0
0
0
1
1
1
1
1
before
0
.
.
.
after
1
0
0
1
1
1
0
0
0
(b) Logical shift r
ight
LShiftR 2,R0
95
Logical Shifts

• Two decimal digits represented in ASCII code are
  located at LOC and LOC1. Pack these two digits
  in a single byte location PACKED.
• Extract the low-order four bits in LOC and LOC1,
  and concatenate them into the single byte at
  PACKED. Example A1, B2?12

Mo
v
e
LOC,R0
R0
points
to
data.
Mo
v
eByte
(R0),R1
Load
first
b
yte
in
to
R1.
LShiftL
4,R1
Shift
left
b
y
4
bit
p
ositions.
Mo
v
eByte
(R0),R2
Load
second
b
yte
in
to
R2.
And
F,R2
Eliminate
high-order
bits.
Or
R1,R2
Concatenate
the
BCD
digits.
Mo
v
eByte
R2,PACKED
Store
the
result.
Figure 2.31. A routine that packs two BCD
digits.
96
Arithmetic Shifts
C
R0
.
.
.
before
0
1
1
0
0
0
1
0
1
.
.
.
after
1
1
1
0
0
1
0
1
1
(c) Ar
ithmetic shift r
ight
AShiftR 2,R0
97
Rotate
98
Multiplication and Division

• Not very popular (especially division)
• Multiply Ri, RjRj ? Ri ? Rj
• 2n-bit product case high-order half in R(j1)
• Divide Ri, Rj Rj ? Ri / Rj
• Quotient is in Rj, remainder may be placed in
  R(j1)

99
Example Programs
100
Vector Dot Product Program
Mo
v
e
A
VEC,R1
R1
p
oin
ts
to
v
ector
A.
Mo
v
e
BVEC,R2
R2
p
oin
ts
to
v
ector
B.
Mo
v
e
N,R3
R3
serv
es
as
a
coun
ter.
Clear
R0
R0
accum
ulates
the
dot
pro
duct.
LOOP
Mo
v
e
(R1),R4
Compute
the
pro
duct
of
Multiply
(R2),R4
next
comp
onen
ts.
Add
R4,R0
Add
to
previous
sum.
Decremen
t
R3
Decremen
t
the
coun
ter.
Branc
h
LOOP
Loop
again
if
not
done.
gt
0
Mo
v
e
R0,DOTPR
OD
Store
dot
pro
duct
in
memory
.
Figure 2.33. A program for computing the dot
product of two vectors.
101
Byte-Sorting Program

• Sort a list of bytes stored in memory into
  ascending alphabetic order.
• The list consists of n bytes, not necessarily
  distinct, stored from memory location LIST to
  LISTn-1. Each byte contains the ASCII code for a
  character from A to Z. The first bit is 0.
• Straight-selection algorithm (compare and swap)

102
Byte-Sorting Program


(j

n
1
j
gt
0
j

j
1)
for



(
k

j
1
k
gt

0
k

k
1
)
for

(LIST
k

gt
LIST
j
)
if

TEMP

LIST
k

LIST
k


LIST

j
LIST
j


TEMP



(a) C-language program for sorting
Mo
v
e
LIST,R0
Load
LIST
in
to
base
register
R0.
Mo
v
e
N,R1
Initialize
outer
lo
op
index

Subtract
1,R1
register
R1
to
j

n
1.
OUTER
Mo
v
e
R1,R2
Initialize
inner
lo
op
index

Subtract
1,R2
register
R2
to
k

j
1.
Mo
v
eByte
(R0,R1),R3
Load
LIST(
j
)
in
to
R3,
whic
h
holds
current
maxim
um
in
sublist.
?
INNER
CompareByte
R3,(R0,R2)
If
LIST(
k
)
R3,
?
Branc
h
0
NEXT
do
not
exhange.
Mo
v
eByte
(R0,R2),R4
Otherwise,
exchange
LIST(
k
)
Mo
v
eByte
R3,(R0,R2)
with
LIST(
j
)
and
load
Mo
v
eByte
R4,(R0,R1)
new
maxim
um
in
to
R3.
Mo
v
eByte
R4,R3
Register
R4
serv
es
as
TEMP
.
NEXT
Decremen
t
R2
Decremen
t
index
registers
R2
and
?
Branc
h
0
INNER
R1,
whic
h
also
serv
e
Decremen
t
R1
as
lo
op
coun
ters,
and
branc
h
Branc
h
gt
0
OUTER
bac
k
if
lo
ops
not
finished.
(b) Assembly language program for sorting
103
Byte-Sorting Program

• The list must have at least two elements because
  the check for loop termination is done at the end
  of each loop.
• If the machine instruction set allows a move
  operation from one memory location directly to
  another memory location

• MoveByte (R0, R2), (R0, R1)MoveByte R3, (R0,
  R2)MoveByte (R0, R1), R3

• MoveByte (R0, R2), R4
• MoveByte R3, (R0, R2)
• MoveByte R4, (R0, R1)
• MoveByte R4, R3

?
104
Linked List

• Many nonnumeric application programs require that
  an ordered list of information items be
  represented and stored in memory in such a way
  that it is easy to add items to the list or to
  delete items from the list at ANY position while
  maintaining the desired order of items.
• Different from Stacks or Queues.

105
Problem Illustration
n
N

• Maintain this list of records in consecutive
  memory locations in some contiguous block of
  memory in increasing order of student ID numbers.
• What if a student withdraws from the course so
  that an empty record slot is created?
• What if another student registers in the course?

Student ID
LIST
Test 1
LIST 4
Student 1
Test 2
LIST 8
Test 3
LIST 12
Student ID
LIST 16
Test 1
Student 2
Test 2
Test 3

106
Linked List

• Each record still occupies a consecutive
  four-word block in the memory.
• But successive records in the order do not
  necessarily occupy consecutive blocks in the
  memory address space.
• Each record contains an address value in a
  one-word link field that specifies the location
  of the next record in order to enable connecting
  the blocks together to form the ordered list.

Link address
Record 1
Record 2
Record
k
0
Head
T
ail
(a) Linking structure
Record 2
Record 1
Ne
w record
(b) Inserting a new record between Record 1 and
Record 2
107
List in Memory
Memory
Key
Link
Data
field
address
field
field
(ID)
(Test scores)
1 word
1 word
3 words
First
Head
27243
1040
2320
Head pointer
record
Second
28106
1200
1040
record
Third
28370
2880
1200
record

Second last
40632
1280
2720
record
Last
47871
0
1280
Tail
record
Figure 2.36. A list of student test scores
organized as a linked list in memory.
108
Insertion of a New Record

• Suppose that the ID number of the new record is
  28241, and the next available free record block
  is at address 2960.
• What are the possibilities of the new records
  position in the list?
• One-entry list
• New head
• Interior positon
• New tail

INSER
TION
Compare
0, RHEAD
Branchgt0
HEAD
ne
w record
Mo
v
e
RNEWREC, RHEAD
becomes a
not empty
one-entry list
Return
Compare
(RHEAD), (RNEWREC)
HEAD
Branchgt0
SEARCH
ne
w record
Mo
v
e
RHEAD, 4(RNEWREC)
insert ne
w record
becomes
Mo
v
e
RNEWREC, RHEAD
some
where after
ne
w head
current head
Return
Mo
v
e
RHEAD, RCURRENT
SEARCH
Mo
v
e
4(RCURRENT), RNEXT
LOOP
Compare
0, RNEXT
Branch0
T
AIL
ne
w record becomes ne
w tail
(RNEXT), (RNEWREC)
Compare
Branchlt0
INSER
T
Mo
v
e
RNEXT
, RCURRENT
insert ne
w record in
an interior position
Branch
LOOP
INSER
T
Mo
v
e
RNEXT
, 4(RNEWREC)
Mo
v
e
RNEWREC, 4(RCURRENT)
T
AIL
Return
109
Deletion of a Record
DELETION
Compare
(RHEAD), RIDNUM
Branchgt0
SEARCH
Mo
v
e
4(RHEAD), RHEAD
not the head record
Return
Mo
v
e
RHEAD, RCURRENT
SEARCH
LOOP
Mo
v
e
4(RCURRENT), RNEXT
Compare
(RNEXT), RIDNUM
Branch0
DELETE
Mo
v
e
RNEXT
, RCURRENT
Branch
LOOP
Mo
v
e
4(RNEXT), R
TEMP
DELETE
R
TEMP
, 4(RCURRENT)
Mo
v
e
Return
Any problem?
Figure 2.38. A subroutine for deleting a record
from a linked list.
110
Encoding of Machine Instructions
111
Encoding of Machine Instructions

• Assembly language program needs to be converted
  into machine instructions. (ADD 0100 in ARM
  instruction set)
• In the previous section, an assumption was made
  that all instructions are one word in length.
• OP code the type of operation to be performed
  and the type of operands used may be specified
  using an encoded binary pattern
• Suppose 32-bit word length, 8-bit OP code (how
  many instructions can we have?), 16 registers in
  total (how many bits?), 3-bit addressing mode
  indicator.
• Add R1, R2
• Move 24(R0), R5
• LshiftR 2, R0
• Move 3A, R1
• Branchgt0 LOOP

8
7
7
10
OP code
Source
Dest
Other info
(a) One-word instruction
112
Encoding of Machine Instructions

• What happens if we want to specify a memory
  operand using the Absolute addressing mode?
• Move R2, LOC
• 14-bit for LOC insufficient
• Solution use two words

OP code
Source
Dest
Other info
Memory address/Immediate operand
(b) Two-word instruction
113
Encoding of Machine Instructions

• Then what if an instruction in which two operands
  can be specified using the Absolute addressing
  mode?
• Move LOC1, LOC2
• Solution use two additional words
• This approach results in instructions of variable
  length. Complex instructions can be implemented,
  closely resembling operations in high-level
  programming languages Complex Instruction Set
  Computer (CISC)

114
Encoding of Machine Instructions

• If we insist that all instructions must fit into
  a single 32-bit word, it is not possible to
  provide a 32-bit address or a 32-bit immediate
  operand within the instruction.
• It is still possible to define a highly
  functional instruction set, which makes extensive
  use of the processor registers.
• Add R1, R2 ----- yes
• Add LOC, R2 ----- no
• Add (R3), R2 ----- yes

115
Encoding of Machine Instructions

• How to load a 32-bit address into a register that
  serves as a pointer to memory locations?
• Solution 1 direct the assembler to place the
  desired address in a word location in a data area
  close to the program, so that the Relative
  addressing mode can be used to load the address.
• Solution 2 use logical and shift instructions
  to construct the desired 32-bit address by giving
  it in parts that are small enough to be
  specifiable using the Immediate addressing mode.

116
Encoding of Machine Instructions

• An instruction must occupy only one word
  Reduced Instruction Set Computer (RISC)
• Other restrictions

OP code
R
i
R
j
Other info
R
k
(c) Three-operand instruction
117
homework

• Page 98 2.1, 2.2, 2.3, 2.8, 2.17(a)(b)(c)

118
homework

• Page 98 2.1, 2.2, 2.3, 2.8, 2.17(a)(b)(c)
• 2.8
• Load A
• Multiply B
• Store RESULT
• .
• Add RESULT
• .

119
(No Transcript)