CS 153 Logic Design Lab

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CS 153Logic Design Lab
Professor Ian G. Harris Department of Computer
Science University of California Irvine
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Purpose of the Course

• Lab companion to CS 151
• Design and simulate combinational and sequential
  logic
• Learn basic Verilog
• Use an industrial simulation tool (Synopsys)
• Understand the internal simulation process to
  appreciate its imprecision

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Reading Material

• No required book.
• Digital Logic Design (CS 151) book is useful
• Some Verilog book is useful (some are on reserve
  at the library)
• Links to Verilog resources are provided on the
  web page

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System Design Flow
Designers Intent Vague idea of behavior known
only to designer.
Intent
Natural Language Specification Complete
behavioral description Written in English (or
other).
Nat. Lang. Spec.
Executable Behavior A simulatable description of
the behavior. Written in a procedural language
(SystemVerilog, SystemC, )
Exec. Behavior
SW Design
Pre-Designed
HW Design
Fabrication
Embedded System
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Hardware Description Languages

• Languages used to describe hardware designs
• Can be used for synthesis or simulation

• Synthesis is manufacturing an Application
  Specific Integrated Circuit (ASIC) or mapping to
  a Field Programmable Gate Array (FPGA)
• Performance/Area/Power are a priority
• Simulation is for the purpose of checking
  functionality
• Simulation must match the real world

• In this class we are doing simulation, not
  synthesis

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Hardware Design
Behavioral Design vs. Structural Design
c a b f d e if (g) out c else
out f

• Behavioral design describes functionality as a
  sequence of steps.
• Structural design describes an interconnection of
  components.

g
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Structural Description, Modules
module T_FF (q, clock, reset) . . . . endmodule

• Represents a physical component, can be
  instantiated many times
• I/O ports declared at the top
• Typically represents a physical component
• Can be structurally connected to other components
• Cannot be invoked like a function

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Instances
module ripple_carry_counter(q, clk,
reset) output 30 q input clk, reset //4
instances of the module TFF are created. TFF
tff0(q0,clk, reset) TFF tff1(q1,q0,
reset) TFF tff2(q2,q1, reset) TFF
tff3(q3,q2, reset) endmodule
module TFF(q, clk, reset) output q input clk,
reset wire d DFF dff0(q, d, clk, reset) not
n1(d, q) endmodule

• TFF is instantated within ripple_carry_counter
• DFF and not are instantiated within TFF
• Structural interconnect is established through
  instantiation

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Testbench (Stimulus Block)
// Control the reset initial begin reset
1'b1 15 reset 1'b0 180 reset 1'b1 10
reset 1'b0 20 stop end // Monitor the
outputs initial monitor(time, " Output q
d", q) endmodule
module stimulus reg clk reg reset wire30
q // instantiate the design block ripple_carry_c
ounter r1(q, clk, reset) // Control the
clock initial clk 1'b0 always 5 clk clk

• The testbench generates the input stimulus
• Observation of data is often included in the
  testbench