F4: Partial RTR Architecture for Qualified HPEC Systems

1
F4 Partial RTR Architecture for Qualified HPEC
Systems

• Dr. Alan D. George
• Professor of ECE, University of Florida
• Ross Hymel
• Ph.D. Student, University of Florida

2
Outline

• Background
• Definitions and acronyms
• Related research
• Misconceptions and motivations
• Project Team Members
• Y1 Tasks
• Milestones and Deliverables
• Conclusions and Member Benefits

3
Background

• Partial reconfiguration (PR) allows multiple
  design modules to time-share the same set of
  physical FPGA resources
• Modules with completely different functions can
  share the same device resources over time
• Partial bitstreams are loaded on the fly, while
  the rest of the device operates uninterrupted

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Definitions and Acronyms

• Partial Reconfiguration Region (PRR)
• Section of FPGA fabric set aside for a PRM.
  Analogous to a keyed socket
• Partial Reconfiguration Module (PRM)
• Design module that is swapped in and out on the
  fly
• A single PRR can have multiple PRMs defined for
  it
• Base Design
• Static portion of the design encompasses all
  non-PRM design resources
• Frame
• Smallest granularity of reconfiguration available
  in a Xilinx part

5
Related Research

• Most previous hardware research has dealt with
  Virtex-II
• V2 architecture not amenable to PR
• Recent (07/2006) tool release now fully supports
  V4 architecture
• V5 will be supported when customer demand
  materializes (2007, according to Xilinx marketing
  department)
• Good portion of PR research in literature focuses
  on theoretical aspects
• Often ignores realities and limitations of real
  hardware
• Relies upon assumptions and unrealistic idealism

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Misconceptions and Motivations

• Misconception 1 Modules can be quickly
  reconfigured
• Absolute fastest reconfiguration speed in V4 is
  3.2 Gb/s gt 1.5 ms to fully reconfigure an LX15
  (150,000 clock cycles _at_ 100 MHz)
• Misconception 2 PRRs can be of any arbitrary
  shape and size
• PRRs must be rectangular and contain an integer
  number of frames
• Misconception 3 PRRs can be placed anywhere on
  chip and moved around
• PRRs may not share a frame, and their location
  and size become frozen after the design is
  finalized
• Misconception 4 PRMs can be swapped into and
  out of different PRRs
• No way to guarantee that clocks and static
  signals that pass through the PRR will enter\exit
  at the same point for different PRMs

• GOAL Investigate experimental realities of
  partial RTR and devise a comprehensive design
  approach to developing RTR systems

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Project Team Members

• Faculty
• Dr. Alan George
• Professor of ECE
• Dr. Herman Lam
• Associate Professor of ECE
• Students
• Ross Hymel student project leader
• 1st-year doctoral student in ECE
• BS in ECE, University of Tulsa, 2006
• NSF Fellow, Alumni Fellow
• Intern at Sandia National Labs
• Mike Rewak
• MS student in ECE
• BS in ECE, University of Florida, 12/2006
• Intern at Sandia National Labs
• TBD
• Optional third graduate student
• Undergraduate student (volunteer) Brandon
  Kilpatrick (honors thesis)

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Overview of Y1 Tasks

• Software/Hardware Tools
• Generic Configuration Controller
• Experimentation and Design Analysis

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Task 1 Software/Hardware Tools

• Master the Xilinx Virtex-4 technology and
  software tools for effective RTR (partial and
  full)
• Select and employ a small set of test experiments
  and case studies as a platform for doing so

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Task 2 Generic Configuration Controller

• Design, implement, and analyze a generic
  configuration controller with run-time support
• Capable of both bitstream loading and
  readback/verification
• Allows for fault-tolerance at device level
  enhanced scrubbing
• Traditional scrubbing is SECDED
• Room for improvement?

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Task 3 Experimentation Design Analysis

• Analyze architectural design options and
  tradeoffs (Safety, Security, Performance,
  Fault-tolerance, etc.)
• Within a framework of mission scenarios selected
  in consultation with supporting members
• Quantify measurable advantages/disadvantages of
  RTR

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Task 4 On-Demand Reconfiguration

• Investigate design methodology/framework to
  simplify dynamic PR system implementation
• Is there a way to simplify the Xilinx PR design
  process at the hardware level to allow rapid
  system development and remote design update by
  people untrained in PR?

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Y1 Milestones, Deliverables, Budget

• Milestones
• Completion of functional config. controller (May
  07)
• Completion of 1-2 case studies (Aug 07)
• Completion of experimentation/analysis and
• formalization of practical scope of RTR (Dec
  07)
• Deliverables
• Midterm and final reports documenting research
  methods, progress, results, and analysis
• Library of generic IP cores, macros, and source
  code developed for use in partial RTR
  applications
• Scholarly conference and/or journal publications
• Budget
• 2-3 CHREC memberships
• 2 memberships allows baseline completion of all
  three tasks
• 3 memberships allows extended set of PR scenarios
  and cases

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Conclusions Member Benefits

• Conclusions
• Self-managed partial RTR offers new and exciting
  opportunities to dramatically increase
  functionality of a single FPGA
• Potential advantages in performance, power, fault
  tolerance, safety, security, real-time, flight
  qualification, adaptive hardware algorithms
• Historically ignored and poorly supported
• Current trends in market position it to be one of
  next frontiers in HPEC gt we need to hit the
  ground running
• Member Benefits
• Direct influence over types of applications,
  missions, and design factors emphasized
• Early access to generic cores and macros intended
  for partial RTR applications
• Research results based upon COTS hardware -
  directly applicable to member interests
• Much reduced learning curve needed for developing
  future partial RTR systems