CHAPTER 4 A PROGRAMMER'S VIEW OF COMPUTER ORGANIZATION

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CHAPTER 4A PROGRAMMER'S VIEW OF COMPUTER
ORGANIZATION
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Two Alternative Input/Output Configurations
CPU coordinates transfer between I/O and memory.
CPU
I/O
Memory
CPU
Memory
I/O
Direct Memory Access (DMA).
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The Central Processing Unit
Control Unit
Address Bus
Program Counter
Memory Address Register
Data Bus
Instruction Register
Memory Data Register
Control Bus
Instruction Decoder
General Purpose Registers
Arithmetic and Logic Unit (ALU)
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The Fetch-Execute Cycle
Program counter provides the address.
Additional instruction bytes retrieved here as
necessary.
Fetch The Next Instruction
Execute the Fetched Instruction
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The Fetch Phase
1.     Memory_Address_Bus ? Program_Counter 2.    
Start Memory Read Operation 3.     Increment
Program_Counter 4.     Wait for Memory Read to
Complete 5.     Instruction_Register ?
Memory_Data_Bus 6.     Go to execute phase.
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Control Flow Portion of a CPU
Memory Data Bus
Control Unit (Opcode decoding and sequencing)
Control Signals
Memory Address Bus
Branch Address
Opcode bits.
Instruction Register
Program Counter
1
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The Intel Processor Family
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Operating Modes of Intel IA

• Real-address Mode This mode corresponds to the
  original 8086 processor and is supported by all
  processors in the IA family. It is the initial
  operating mode when a hardware reset signal is
  applied to the processor at start-up. Only a
  limited number of processor features are
  available in real mode and the physical address
  space is limited to one megabyte.
• Protected Mode 
• System Management Mode

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Operating Modes of Intel IA

• Real-address Mode 
• Protected Mode This mode was originally
  introduced with the Intel 286, and later enhanced
  in the Intel 386. Protected mode offers greater
  performance than real mode. All of the features
  of the processor are available and a much larger
  physical address space.
• System Management Mode

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Operating Modes of Intel IA

• Real-address Mode 
• Protected Mode
• System Management Mode This mode was originally
  introduced with the Intel 386SL. This mode is
  primarily used to implement power management and
  system security. It is not described in this
  text.

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Four Types of Instruction Operands

• A constant embedded within the instruction
  representation, or
• The contents of a register, or
• The contents of a memory location, or
• The contents of an I/O port.

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Instruction Formats
Source operand
Destination operand
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General Purpose Registers
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Segment Registers
Hidden Part
Visible Part
31
0
16 15
Base Address, Limit, and Access
Information(not used in Real Mode)
Segment Selector
15
EFlags and EIP Registers
0
31
16
Flags Register
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Byte Ordering of 32-bit Value With Little Endian
Format.
32-bit value 1234567816
0001 0010
0011 0100
0101 0110
0111 1000
Byte N3
Byte N2
Byte N1
Byte N
In little endian format, the address of a 32-bit
quantity is the same as the address of its least
significant byte.
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The Stack
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Real-Mode Addressing
16-bit segment
0000
16-bit offset
12
MSBs of offset
4
LSBs
padded with four 0's
of offset
on the left
16-bit Adder
16
MSBs
4
LSBs
of result
of result
20-bit physical address
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Real-Mode Addressing
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Instruction Operands

• Constant
• Immediate Mode
• Embedded within representation of instruction.
• Register
• Register Mode
• I/O Port

• Memory Location
• Real Mode
• Address RB RI constant
• Protected Mode
• Address R1 C1 ? R2 C2

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Immediate Mode(Example MOV AX,12345)
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Instruction Operands

• Constant
• Immediate Mode
• Embedded within representation of instruction.
• Register
• Register Mode
• I/O Port

• Memory Location
• Real Mode
• Address RB RI constant
• Protected Mode
• Address R1 C1 ? R2 C2

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Register Mode(Example MOV AX,CX)
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Instruction Operands

• Constant
• Immediate Mode
• Embedded within representation of instruction.
• Register
• Register Mode
• I/O Port

• Memory Location
• Real Mode
• Address RB RI constant
• Protected Mode
• Address R1 C1 ? R2 C2

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ADDRESSING MEMORYINREAL MODE
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Real Mode Defaults

• Address Field of Instructions is 16 bits
• Precede instruction by 0x67 to use 32 bits
• DB 67H
• MOV AX,BX
• Operands are either 8 or 16 bits
• Precede instruction by 0x66 to use 32 bits
• DB 66H
• MOV AX,BX

Equivalent to MOV AX,EBX
Equivalent to MOV EAX,BX
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Real-Mode Addressing
Base
Index
Constant
BX BP None
16-bit 8-bit None
SI DI None


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Direct Addressing Mode(Example MOV AX,TOTAL)
opcode
16-bit offset
Instruction provides
memory
offset
operand
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Register Indirect Mode(Example MOV AX,BX)
opcode
code
memory
BX, BP, SI, or DI
operand
Register provides offset
or
Address RB RI constant
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Indexed and Based Address Mode(Example MOV
AX,BX3)
opcode
code
displacement
Offset is sum of selected
memory
register and displacement.
Code selects
register to use

operand
BX, BP, SI, DI
Based BX or BP
Indexed SI or DI
Address RB RI constant
or
Address RB RI constant
32
Based-indexed Address Mode(Example MOV
AX,BXSI3)
Address RB RI constant
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ADDRESSING MEMORYINPROTECTED MODE
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Protected Mode Defaults

• Address Field of Instructions is 32 bits
• Precede instruction by 0x67 to use 16 bits
• DB 67H
• MOV EAX,EBX
• Operands are either 8 or 32 bits
• Precede instruction by 0x66 to use 16 bits
• DB 66H
• MOV EAX,EBX

Equivalent to MOV EAX,BX
Equivalent to MOV AX,EBX
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How Segment Registers are Used
Global Descriptor Table
GDTR Register
Resides in Main Memory
Physical Address ( Length) of Global Descriptor
Table
32 bits
32 bits

Segment Start Address
. . .
16 bits
PhysicalAddress
Segment Register

16-bit Segment Selector
32-bit offset from effective address calculation
32 bits
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The Flat Memory Model

• GDT configured so that all segments start at
  physical address zero and have a size of 4GB.
• There's a one-to-one correspondence between
  physical addresses and the 32-bit offsets
  produced by effective address calculations.
• Memory looks like a single continuous space,
  called a linear address space.

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Instruction Operands

• Constant
• Immediate Mode
• Embedded within representation of instruction.
• Register
• Register Mode
• I/O Port

• Memory Location
• Real Mode
• Address RB RI constant
• Protected Mode
• Address R1 C1 ? R2 C2

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Protected-Mode Addressing
Base
Index
Scale Factor
Displacement
EAX EBX ECX EDX ESI EDI EBP ESP None
EAX EBX ECX EDX ESI EDI EBP None
1 2 3 4
None 8-bit 16-bit 32-bit
?


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Restrictions MOV dst,src

• No more than 1 operand in memory.
• No more than 1 operand in a segment register.

• Only 8, 16, or 32 bit operands.
• Operand sizes must match (or else extend the
  length using MOVSX or MOVZX).

• If destination is a segment register, source
  cannot be an immediate constant.

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Operand Sizes

• May be implicit INC EAX
• Size of register EAX is 32 bits.
• May be inferred MOV AL,EBX
• AL is 8 bits, so register EBX contains the
  address of an 8-bit memory operand.
• May be explicit INC DWORD EBX
• Ambiguous without DWORD!

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Data Movement Instructions

• MOV dst,src dst ? src
• LEA reg32,mem reg32 ? offset32 (mem)
• MOVZX reg32,src reg32 ? zero extended src
• MOVSX reg32,src reg32 ? sign extended src
• XCHG dst,src temp ? dst
• dst ? src
• src ? temp

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Stack Instructions

• PUSH src16 ESP ? ESP-2, MEMSSESP ? src16
• PUSH src32 ESP ? ESP-4, MEMSSESP ? src32
• PUSHF ESP ? ESP-4, MEMSSESP ? EFlags
• PUSHA Pushes EAX, ECX, EDX, EBX, ESP, EBP, ESI,
  EDI
• POP dst16 dst16 ? MEMSSESP, ESP ? ESP2
• POP dst32 dst32 ? MEMSSESP, ESP ? ESP4
• POPF EFlags ? MEMSSESP, ESP ? ESP4
• POPA Pops EDI, ESI, EBP, skip, EBX, EDX, ECX,
  EAX

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Arithmetic Instructions

• ADD dst,src
• ADC dst,src
• SUB dst,src
• SBB dst,src
• INC dst
• DEC dst
• NEG dst

• MUL src unsigned
• IMUL src signed
• DIV src unsigned
• IDIV src signed
• CBW
• CWD/CDQ
• CMP dst,src

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Bitwise Logical Instructions

• AND dst,src dst ? dst src
• OR dst,src dst ? dst src
• XOR dst,src dst ? dst src
• NOT dst dst ? dst
• TEST dst,src dst src

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Shift Instructions opc dst,count

• RCL
• ROL
• SAL
• SHL

• RCR
• ROR
• SAR
• SHR

0
0
0
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Conditional Jump Instructions

• Signed Tests
• JG/JNLE label
• JGE/JNL label
• JL/JNGE label
• JLE/JNG label
• Equality Tests
• JE/JZ label
• JNE/JNZ label

• Unsigned Tests
• JA/JNBE label
• JAE/JNB label
• JB/JNAE label
• JBE/JNA label
• Other Tests
• JC, JNC, JO, JNO, JS, JNS, JPO, JNP, JCXZ

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Other Jump Instructions

• Unconditional
• JMP label
• JMP regptr
• JMP memptr

• Loops (count in register ECX)
• LOOP short-label
• LOOPE/LOOPZ short-label
• LOOPNE/LOOPNZ short-label