CS61C Lecture 13

1
CS152 Computer Architecture andEngineeringLec
ture 7 Single Cycle Control
2003-09-16 Dave Patterson (www.cs.berkeley.edu/
patterson) www-inst.eecs.berkeley.edu/cs152/
2
Review

• 5 steps to design a processor
• 1. Analyze instruction set gt datapath
  requirements
• 2. Select set of datapath components establish
  clock methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to
  determine setting of control points that effects
  the register transfer.
• 5. Assemble the control logic (This Lecture)
• MIPS makes it easier
• Instructions same size Source registers,
  immediates always in same place
• Operations always on registers/immediates
• Single cycle datapath gt CPI1, CCT gt long
• On-line Design Notebook
• Open a window and keep an editor running while
  you workcutpaste
• Former CS 152 students (and TAs) say they use
  on-line notebook for programming as well as
  hardware design one of most valuable skills
•   Refer to the handout as an example

3
Recap The MIPS-lite Subset

• ADD and subtract
• add rd, rs, rt
• sub rd, rs, rt
• OR Imm
• ori rt, rs, imm16
• LOAD and STORE
• lw rt, rs, imm16
• sw rt, rs, imm16
• BRANCH
• beq rs, rt, imm16

4
Recap A Single Cycle Datapath

• Rs, Rt, Rd and Imed16 hardwired into datapath
  from Fetch Unit
• We have everything except control signals
  (underline)
• Todays lecture will show you how to generate the
  control signals

Instructionlt310gt
PCSrc
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr
ALUctr
5
5
5
Zero
MemtoReg
MemWr
busA
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
5
Meaning of the Control Signals

• MemWr 1 ? write memory
• MemtoReg 0 ? ALU 1 ? Mem
• RegDst 0 ? rt 1 ? rd
• RegWr 1 ? write register

• ExtOp zero, sign
• ALUsrc 0 ? regB 1 ? immed
• ALUctr add, sub, or

RegDst
ALUctr
MemtoReg
MemWr
Equal
Rt
Rd
0
1
Rs
Rt
RegWr
5
5
5
busA

Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
0
32
busB
32
0
32
Mux
Mux
Clk
32
WrEn
Adr
1
1
Data In
Extender
Data Memory
imm16
32
16
Clk
ExtOp
ALUSrc
6
This lecture vs. Chapter 5 Beta 3/e

• Book
• MIPS-lite subset
• AddU, SubU, LW, SW
• BEQ, OR
• AND, SLT, J
• Control lines names
• MemtoReg, PCSrc, ALUSrc, RegDst
• MemWrite, RegWrite
• No ExtOp since subset immediates sign extend
• ALUoperation 4 bits
• MemRead MemWrite

• This lecture
• MIPS-lite subset
• AddU, SubU, LW, SW
• BEQ, ORI
• Control lines names
• MemtoReg, PCSrc, ALUSrc, RegDst
• MemWr, RegWr
• ExtOp (zero extend or sign extend)
• ALUctr 3 bits (no NOR)
• MemWr0 gt MemRead

7
The Add Instruction

• add rd, rs, rt
• memPC Fetch the instruction from memory
• Rrd lt Rrs Rrt The actual operation
• PC lt PC 4 Calculate the next
  instructions address

8
Instruction Fetch Unit at the Beginning of Add

• Fetch the instruction from Instruction memory
  Instruction lt memPC
• This is the same for all instructions

Instructionlt310gt
PCSrc
4
00
PC
Clk
imm16
PC Ext
9
The Single Cycle Datapath during Add

• Rrd lt Rrs Rrt

Instructionlt310gt
PCSrc 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 1
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 1
5
5
5
MemtoReg 0
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 0
ExtOp x
10
Instruction Fetch Unit at the End of Add

• PC lt PC 4
• This is the same for all instructions except
  Branch and Jump

Instructionlt310gt
PCSrc
4
0
00
PC
1
Clk
imm16
11
Two equivalent ways to specify control
(Rotate about 45degree axis)

• Book does left version (Fig 5.18)
• Well do right version by committee and
  transmiter, one control at a time

12
Setting PC Source Control Signal

• PCSrc 0 ? PC lt PC 4 1 ? PC lt PC 4
  SignExt(Im16), 2b00
• Later in lecture higher-level connection between
  mux and branch cond

13
Meaning of the Control Signals

• MemWr 1 ? write memory
• MemtoReg 0 ? ALU 1 ? Mem
• RegDst 0 ? rt 1 ? rd
• RegWr 1 ? write register

• ExtOp 0 ? zero 1 ? sign
• ALUsrc 0 ? regB 1 ? immed
• ALUctr add, sub, or

RegDst
ALUctr
MemtoReg
MemWr
Equal
Rt
Rd
0
1
Rs
Rt
RegWr
5
5
5
busA

Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
0
32
busB
32
0
32
Mux
Mux
Clk
32
WrEn
Adr
1
1
Data In
Extender
Data Memory
imm16
32
16
Clk
ExtOp
ALUSrc
14
Administrivia

• Office hours in Lab
• Mon 4 530 Jack, Mon 3 430 John
• Daves office hours Tue 330 5
• Reading Sections 5.6, 5.8, 5.11, 5.12 in Beta ed.

15
Specify ALU source mux Control

• ALUsrc 0 ? reg as ALU B input 1 ? immediate as
  ALU B input

Rt
Rd
0
1
Rs
Rt
5
5
5
busA

Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
32
busB
0
32
Mux
Clk
32
1
Data In
Extender
imm16
32
16
ExtOp
ALUSrc
16
Specify Immediate Extender Op Control

• ExtOp 0 ? zero extend immediate 1 ? sign
  extend imm.

Rt
Rd
0
1
Rs
Rt
5
5
5
busA

Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
32
busB
0
32
Mux
Clk
32
1
Data In
Extender
imm16
32
16
ExtOp
ALUSrc
17
Specify Register Write Control

• RegWr 1 ? write register

RegDst
Rt
Rd
0
1
Rs
Rt
RegWr
5
5
5
busA

Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
32
busB
32
0
32
Mux
Clk
1
Extender
imm16
32
16
ALUSrc
ExtOp
18
Specify Register Destination Control

• RegDst 0 ? rt 1 ? rd

RegDst
Rt
Rd
0
1
Rs
Rt
RegWr
5
5
5
busA

Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
32
busB
0
32
Mux
Clk
1
Extender
imm16
32
16
ALUSrc
ExtOp
19
Specify the Memory Write Control Signal

• MemWr 1 ? write memory

busW
20
Specify Memory To Register File Mux Control

• MemtoReg 0 ? ALU 1 ? Mem

busW
21
Specify the ALU Control Signals

• ALUctr 0 ? add, 1 ? sub, 2 ? or

busW
22
Instruction Fetch Unit at the End of Branch

• if (Zero 1) PC PC 4 SignExtimm16,
  2b00 else PC PC 4

Instructionlt310gt
PCSrc

• What is encoding of PCSrc?
• Direct MUX select?
• Branch / not branch
• Lets choose second option

Zero
PCSrc
4
0
00
PC
1
Clk
imm16
23
The Single Cycle Datapath during Or Immediate

• Rrt lt Rrs or ZeroExtImm16

Instructionlt310gt
PCSrc 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 0
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr Or
RegWr 1
5
5
5
MemtoReg 0
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 1
ExtOp 0
24
The Single Cycle Datapath during Load

• Rrt lt Data Memory Rrs SignExtimm16

Instructionlt310gt
PCSrc 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 0
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 1
5
5
5
MemtoReg 1
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
32
imm16
32
16
Clk
ALUSrc 1
ExtOp 1
25
The Single Cycle Datapath during Store

• Data Memory Rrs SignExtimm16 lt Rrt

Instructionlt310gt
PCSrc
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr
RegWr
5
5
5
MemtoReg
busA
Zero
MemWr
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
26
The Single Cycle Datapath during Store

• Data Memory Rrs SignExtimm16 lt Rrt

Instructionlt310gt
PCSrc 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst x
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 0
5
5
5
MemtoReg x
busA
Zero
MemWr 1
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
32
Data In
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 1
ExtOp 1
27
The Single Cycle Datapath during Branch

• if (Rrs - Rrt 0) Zero lt 1 else
  Zero lt 0

Instructionlt310gt
PCSrc Br
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst x
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr Sub
RegWr 0
5
5
5
MemtoReg x
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 0
ExtOp x
28
Step 4 Given Datapath RTL -gt Control
Instructionlt310gt
Inst Memory
lt2125gt
lt2125gt
lt1620gt
lt1115gt
lt015gt
Adr
Op
Fun
Imm16
Rd
Rs
Rt
Control
ALUctr
MemtoReg
MemWr
ALUSrc
RegDst
ExtOp
RegWr
Zero
PCSrc
DATA PATH
29
A Summary of Control Signals
inst Register Transfer ADD Rrd lt Rrs
Rrt PC lt PC 4 ALUsrc RegB, ALUctr
add, RegDst rd, RegWr, PCSrc 4 SUB Rrd
lt Rrs Rrt PC lt PC 4 ALUsrc RegB,
ALUctr sub, RegDst rd, RegWr, PCSrc
4 ORi Rrt lt Rrs zero_ext(Imm16) PC lt
PC 4 ALUsrc Im, Extop Z, ALUctr or,
RegDst rt, RegWr, PCSrc 4 LOAD Rrt lt
MEM Rrs sign_ext(Imm16) PC lt PC 4
ALUsrc Im, Extop Sn, ALUctr add,
MemtoReg, RegDst rt, RegWr, PCSrc
4 STORE MEM Rrs sign_ext(Imm16) lt
Rrs PC lt PC 4 ALUsrc Im, Extop Sn,
ALUctr add, MemWr, PCSrc 4 BEQ if (
Rrs Rrt ) then PC lt PC sign_ext(Imm16)
00 else PC lt PC 4 PCSrc Br, ALUctr
sub
30
A Summary of the Control Signals
func
10 0000
See
10 0010
We Dont Care -)
Appendix A
op
00 0000
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
31
The Concept of Local Decoding
func
ALUctr
op
6
Main Control
3
ALUop
6
N
ALU
32
The Encoding of ALUop

• In this exercise, ALUop has to be 2 bits wide to
  represent
• (1) R-type instructions
• I-type instructions that require the ALU to
  perform
• (2) Or, (3) Add, and (4) Subtract
• To implement the more of MIPS ISA, ALUop has to
  be 3 bits to represent (4 bits in book to include
  NOR)
• (1) R-type instructions
• I-type instructions that require the ALU to
  perform
• (2) Or, (3) Add, (4) Subtract, and (5) And
  (Example andi)

33
The Decoding of the func Field
34
The Truth Table for ALUctr
functlt30gt
Instruction Op.
0000
add
0010
subtract
0100
and
0101
or
1010
set-on-less-than
35
The Logic Equation for ALUctrlt2gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt2gt
0
x
1
x
x
x
x
1
1
x
x
0
0
1
0
1
1
x
x
1
0
1
0
1
This makes funclt3gt a dont care

• (ALUctrlt2gt ! ALUoplt2gt) ALUoplt0gt
• ALUoplt2gt !funclt2gt funclt1gt
  !funclt0gt

36
The Logic Equation for ALUctrlt1gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt1gt
0
0
0
x
x
x
x
1
0
x
1
x
x
x
x
1
1
x
x
0
0
0
0
1
1
x
x
0
0
1
0
1
1
x
x
1
0
1
0
1

• (ALUctrlt1gt !ALUoplt2gt) !ALUoplt1gt
• ALUoplt2gt !funclt2gt !funclt0gt

37
The Logic Equation for ALUctrlt0gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt0gt
0
1
x
x
x
x
x
1
1
x
x
0
1
0
1
1
1
x
x
1
0
1
0
1

• ALUctrlt0gt !ALUoplt2gt ALUoplt1gt
• ALUoplt2gt !funclt3gt funclt2gt
  !funclt1gt funclt0gt
• ALUoplt2gt funclt3gt !funclt2gt
  funclt1gt !funclt0gt

38
The ALU Control Block

• ALUctrlt2gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt2gt funclt1gt
  !funclt0gt
• ALUctrlt1gt !ALUoplt2gt !ALUoplt1gt
• ALUoplt2gt !funclt2gt !funclt0gt
• ALUctrlt0gt !ALUoplt2gt ALUoplt1gt
• ALUoplt2gt !funclt3gt funclt2gt
  !funclt1gt funclt0gt
• ALUoplt2gt funclt3gt !funclt2gt
  funclt1gt !funclt0gt

39
Step 5 Logic for each control signal

• PCSrc lt (OP BEQ) ? Br plus4
• ALUsrc lt (OP Rtype) ? regB immed
• ALUctr lt (OP Rtype) ? funct (OP
  ORi) ? ORfunction (OP BEQ) ?
  SUBfunction ADDfunction
• ExtOp lt _____________
• MemWr lt _____________
• MemtoReg lt _____________
• RegWr lt_____________
• RegDst lt _____________

40
Step 5 Logic for each control signal

• PCSrc lt (OP BEQ) ? Br plus4
• ALUsrc lt (OP Rtype) ? regB immed
• ALUctr lt (OP Rtype) ? funct (OP
  ORi) ? ORfunction (OP BEQ) ?
  SUBfunction ADDfunction
• ExtOp lt (OP ORi) ZEROextend
  SIGNextend
• MemWr lt (OP Store) ? 1 0
• MemtoReg lt (OP Load) ? 1 0
• RegWr lt ((OP Store) (OP BEQ)) ? 0
  1
• RegDst lt ((OP Load) (OP ORi)) ? 0
  1

41
The Truth Table for the Main Control
op
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
R-type
ori
lw
sw
beq
jump
RegDst
1
0
0
x
x
x
ALUSrc
0
1
1
1
0
x
MemtoReg
0
0
1
x
x
x
RegWrite
1
1
1
0
0
0
MemWrite
0
0
0
1
0
0
PCSrc
0
0
0
0
1
0
Jump
0
0
0
0
0
1
ExtOp
x
0
1
1
x
x
ALUop (Symbolic)
R-type
Or
Add
Add
xxx
Subtract
ALUop lt2gt
1
0
0
0
x
0
ALUop lt1gt
0
1
0
0
x
0
ALUop lt0gt
0
0
0
0
x
1
42
The Truth Table for RegWrite
op
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
R-type
ori
lw
sw
beq
jump
RegWrite
1
1
1
0
0
0

• RegWrite R-type ori lw
• !oplt5gt !oplt4gt !oplt3gt !oplt2gt !oplt1gt
  !oplt0gt (R-type)
• !oplt5gt !oplt4gt oplt3gt oplt2gt !oplt1gt
  oplt0gt (ori)
• oplt5gt !oplt4gt !oplt3gt !oplt2gt oplt1gt
  oplt0gt (lw)

RegWrite
43
PLA Implementation of the Main Control
RegWrite
ALUSrc
RegDst
MemtoReg
MemWrite
Branch
Jump
ExtOp
ALUoplt2gt
ALUoplt1gt
ALUoplt0gt
44
A Real MIPS Datapath (CNS T0)
45
Putting it All Together A Single Cycle Processor
ALUop
ALU Control
ALUctr
3
func
RegDst
op
3
Main Control
Instrlt50gt
6
ALUSrc
6

Instrlt3126gt
Instructionlt310gt
PCSrc
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr
RegWr
5
5
5
MemtoReg
busA
MemWr
Zero
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Instrlt150gt
Clk
ALUSrc
ExtOp
46
Drawback of this Single Cycle Processor

• Long cycle time
• Cycle time must be long enough for the load
  instruction
• PCs Clock -to-Q
• Instruction Memory Access Time
• Register File Access Time
• ALU Delay (address calculation)
• Data Memory Access Time
• Register File Setup Time
• Clock Skew
• Cycle time for load is much longer than needed
  for all other instructions

47
Preview

• Next Time
• MultiCycle Data Path
• CPI ? 1, CycleTime much shorter (1/5 of time)

48
Summary

• Single cycle datapath gt CPI1, CCT gt long
• 5 steps to design a processor
• 1. Analyze instruction set gt datapath
  requirements
• 2. Select set of datapath components establish
  clock methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to
  determine setting of control points that effects
  the register transfer.
• 5. Assemble the control logic
• Control is the hard part
• MIPS makes control easier
• Instructions same size
• Source registers always in same place
• Immediates same size, location
• Operations always on registers/immediates

Processor
Input
Control
Memory
Output
49
Where to get more information?

• Chapter 5.1 to 5.4 of your text book
• David Patterson and John Hennessy, Computer
  Organization Design The Hardware / Software
  Interface, Third Edition, Morgan Kaufman
  Publishers, San Mateo, California, 2003.
• One of the best PhD thesis on processor design
• Manolis Katevenis, Reduced Instruction Set
  Computer Architecture for VLSI, PhD
  Dissertation, EECS, U C Berkeley, 1982.
• For a reference on the MIPS architecture
• Gerry Kane, Joe Heinrich MIPS RISC
  Architecture, Prentice Hall, 2nd edition, 1992