VHDL to PlaceandRoute Design Flow Tutorial

1
VHDL to Place-and-Route Design Flow Tutorial
Mississippi State University Dallas Semiconductor

• By Wei Lii Tan
• Advisor Dr. Robert Reese
• This revision October 28, 2001

2
Major Changes in This Revision

• Deleted all references to Design Planner.
• Edited design flow to use Silicon Ensemble for
  floorplanning, Qplace and Wroute.
• Added explanation for Display Options and Find
  forms.
• Added section on checking for shorts between VDD
  and GND in the ICFB section.

3
Introduction

• This tutorial will guide you through the
  synthesis of a fully placed-and-routed design
  from a VHDL entity.
• The tutorial will use the following CAD tools
• - Synopsys Design Compiler
• - Cadence Silicon Ensemble
• - Cadence ICFB
• - Modelsim QHDL

4
Introduction

• The following conventions will be used in this
  tutorial
• - File names will be in italics, e.g.
  /ccs/issl/micro/users/tan/myfile.vhd
• - User input (e.g. what you need to type) will
  be in boldface, e.g. type swsetup cadence-ncsu

5
The Example Design

• The design we will be using as an example for
  this tutorial is a VHDL model of a Dallas
  Semiconductor DS1620k temperature sensing kit.
• The interface reads the temperature from the
  DS1620k, then outputs the data to a seven-segment
  digit display.
• The design also includes some simple gates for
  debugging, such as a NAND gate, NOR gate,
  inverter, and a DFF.
• A simple counter is included in the design too.

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The Example Design

• The main top-level signals in the design are
• inv_in, inv_out input and output for simple
  inverter
• nand2in_a, nand2in_b, nand2_out inputs and
  output for simple NAND gate.
• nor2in_a, nor2in_b, nor2_out inputs and output
  for simple NOR gate.
• _csb_6_ to _csb_0_ Signals for MSB of the
  seven-segment digit display.
• _lsb_6_ to _lsb_0_ Signals for LSB of the
  seven-segment digit display.

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Copying Example Files

• Copy the entire directory /ccs/issl/micro/users/ta
  n/tutorials/design_flow into your work directory
• importantAll directories will start with
  your_work_directory/design_flow, unless specified
  otherwise.

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Design Flow
VHDL Model
VHDL -gt Verilog Conversion
Synopsys Design Compiler
Verilog Model
Verilog Verification
Modelsim
Verilog Model
Place-and-Route
Cadence Silicon Ensemble
DEF File
Export to Other Formats, SPICE Verification
Cadence ICFB
Verilog Model
Verilog Verification
Modelsim
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Synopsys Design Compiler

• This tool will convert a VHDL model to a Verilog
  model. It requires the use of the following
  user-provided files
• - Library file, in .db format.
• - Script file (file extension .script)
• - The VHDL file to be converted to Verilog.
• At this stage, we will be using Design Compiler
  to generate a Verilog model, without pads, of a
  VHDL file called topchip_gold_nopads.

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Synopsys Design Compiler

• The VHDL file that we will be using is
  topchip_nopads.vhd.
• Using a script file with Design Compiler, we will
  convert this VHDL model to verilog.
• The next page shows the script file used to
  compile topchip_nopads.vhd. The script file is
  called topchip_nopads.script

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Synopsys Design Compiler Script File

• link_librarytarget_libraryjennings_pads_noqn.db
  
• define_design_lib tempsense -path
  /ccs/issl/micro/users/tan/dallas1/sc_tests/myfiles
  /vhdl2/rtl/tempsense
• analyze -work tempsense -f vhdl
  ../rtl/tempsense/topchip_final_components.vhd
  ../rtl/tempsense/bin2bcd_mod.vhd
  ../rtl/tempsense/pulse.vhd ../rtl/tempsense/twosco
  mp.vhd ../rtl/tempsense/sev_seg_display.vhd
  ../rtl/tempsense/ds1620_i.vhd ../rtl/tempsense/sim
  ple_gate.vhd ../rtl/tempsense/topchip_count4.vhd
• read -f vhdl ../rtl/tempsense/topchip_gold_nopads.
  vhd
• set_flatten true
• max_area 0.0
• current_design topchip_gold_nopads
• compile -ungroup_all -map_effort medium
• dont_touch_network CLK
• dont_touch_network clk
• dont_touch_network find(pin, /r)
• set_max_fanout 8.0 find(design,
  topchip_gold_nopads)
• compile -incremental_mapping -map_effort medium
• check_design
• verilogout_single_bit true
• write -f verilog -output ../gate/topchip_gold_nopa
  ds_noqn.v
• quit

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Why use a script file?

• Using a script file with dc_shell is equivalent
  to typing the exact commands in dc_shell
  interactively.
• A script file automates the process of typing in
  all the commands manually.

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What is the .db file for?

• The database (.db) file holds information about
  the standard cell library used to implement the
  VHDL design.
• It provides information about the standard cells
  the names of the standard cells, input/output
  ports, as well as timing characteristics and
  functionality.

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Design Compiler

• Change to the directory synopsys/run_syn
• Type swsetup synopsys
• Type dc_shell f topchip_nopads.script
• The -f option tells design compiler to use a
  script file, and not run in interactive mode.
• 5. After design compiler finishes (it should take
  about 5 minutes to finish the compilation), a
  verilog netlist file called topchip_nopads.v
  should be created in the directory synopsis/gate.

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Design Compiler

• Note If a verilog netlist file with the same
  name exists in the target directory, design
  compiler will overwrite it.
• Now that we have a verilog file, our next step
  would be to simulate the verilog netlist to check
  for errors.

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Modelsim

• The next step in the design flow is simulating
  the verilog netlist that was generated using
  Synopsys Design Compiler.
• Change to the qhsim directory, and type swsetup
  modelsim.
• If the qhsim/work directory does not exist,
  create one by typing qhlib work.
• - The qhlib work command creates a directory
  called work, and also stores Modelsim
  information in the work directory. This
  directory will be the object directory for
  standard cells and top-level designs that are
  compiled using Modelsim.

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Modelsim

• Before we compile our top-level design
  (topchip_nopads.v), we need to compile the
  standard cells that make up topchip_nopads.v. In
  the qhsim directory, type
• qvlcom ../synopsys/gate/libcells.v.
• 4. Type
• qvlcom ../synopsys/gate/topchip_nopads.v. This
  will compile our top-level design file.
• 5. Now, type
• qvlcom ../synopsys/gate/tb_topchip_nopads.v.
  This will compile the testbench for our design.
  The testbench supplies input vectors needed to
  test the functionality of our design.

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Modelsim

• To enter Qhsim and simulate our design, type
  qhsim tb_topchip_nopads. Note that the argument
  after the qhsim command refers to the Verilog
  module name of our design, not the file name.
• After you do step 6, you should see a screen that
  looks like Figure 1. In the command window, type
  view signals ltentergt and view wave ltentergt. These
  commands bring up the signals and waves windows
  respectively.

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Figure 1 Modelsim Command Window
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Modelsim

• 8. Go to the signals window, click on view -gt
  wave -gt signals in region. This will add all the
  top-level signals to the wave window.
• 9. Type run 150 us in the command window. This
  will run the testbench for 150 microseconds.
• 10. Note that all the commands that you entered
  in the command window can be entered into a text
  file, then recalled by typing do filename in the
  command window.

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Figure 2 Simulation Results Waveform
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Silicon Ensemble

• We will now move on to using Silicon Ensemble.
• 1. Make sure that you are in the
  cadence/dp_se/run directory.
• 2. In the terminal window, type
• swsetup cadence-se
• sedsm
• This will start Silicon Ensemble.

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Importing the LEF File (Silicon Ensemble)

• 1. In Silicon Ensemble, click on File -gt Import
  -gt LEF.
• 2. In the Import LEF form, select the file
  ../tech/jennings_ami06_pads_noqn.lef, then click
  on OK.

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Importing a Verilog netlist into Silicon Ensemble

• In the main window, click on File -gt Import -gt
  Verilog
• Click on Browse to choose the verilog source
  file.
• Add the file synopsys/gate/libcells.v by
  double-clicking on that file, and then clicking
  on OK in the File form.

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Figure 3 The File Form
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Importing a Verilog netlist into Silicon Ensemble

• Back in the Import Verilog form, fill in the
  information according to Figure 4. Then, click on
  OK.
• This will import the standard cell information
  into Silicon Ensemble.

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Figure 4 The Input Verilog Form
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Importing a Verilog netlist into Silicon Ensemble

• Now, click on File -gt Import -gt Verilog again.
• Click on Browse. In the File form, delete (by
  pressing the DEL button) the libcells.v from
  the selected files list, and add
  cadence/dp_se/netlist/topchip_nopads.v into the
  selected files list.
• Click on OK.

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Importing a Verilog netlist into Silicon Ensemble

• In the Import Verilog form, type topchip_nopads
  for the Verilog Top Module, and add
  jennings_ami06_pads_noqn to the Compiled
  Verilog Reference Libraries. The rest of the
  information stays the same. (Refer Figure 5, next
  slide).
• Click on Yes when Silicon Ensemble asks if it
  is okay to overwrite the original content of the
  reference library we will not be destroying
  data, just adding to it.

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Figure 5 The Input Verilog Form
31
Floorplanning

• In the main window, click on Flooplan -gt
  Initialize Floorplan.
• In the Initialize Floorplan window, click on the
  Variables button. Another window, the Environment
  Variables form, will pop up.
• In the Environment Variables form, change the
  variable PLAN.LOWERLEFT.ORIGIN to TRUE.
• Click on OK in the Environmental Variables form.

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Figure 6 The Environment Variables Form
33
Floorplanning

• In the Init Floorplan form, set IO to Core
  Distance to 40.00 microns for both Left/Right and
  Top/Bottom.
• Make sure the Flip every other row and Abut
  Rows boxes are checked.
• Also, make sure all the other information is
  entered according to Figure 7 on the next slide.
• If you press the Help button, you will get a
  detailed explanation on what all the options
  mean.
• Finally, hit the OK button.

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Figure 7 The Init Floorplan Form
35
Figure 8 After Floorplan Initialization
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Floorplanning

• We still need to add rows for the double-height
  cells. In the main window, click on Edit -gt Add
  -gt Row
• In the Add Row window, select dbl_core as the
  Site Type, and check the Flip and Abut Every
  Other Row boxes.
• Click on the Area button. Then, click and drag,
  in the main window, an area that approximately
  covers all of the original row area. After you do
  this the X-Y values should be filled in
  automatically.
• Click on the OK button.

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Figure 9 The Add Row Form
38
Figure 10 After Adding Rows for Double-Height
Cells.
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Floorplanning

• Finally, in the main window, click on File -gt
  Save as
• Save the design as fplan.

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Adding Supply Rings

• In the main window, click on Route -gt Plan Power.
• In the Plan Power window, click on the Add Rings
  button.
• In the PP Add Rings window, change both the
  horizontal and vertical Core Ring Width to 4.50.
  Core Ring Width refers to the width of the supply
  rings that are between the I/O and Core sections.
• Click on Help to get detailed explanations on all
  the fields.
• Click on OK in the PP Add Rings form, and click
  on Close in the Plan Power form.

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Figure 11 After Adding Supply Rings.
42
Adding Pins

• To add top-level pins to the layout, click on
  Place -gt Ios in the main window.
• Choose random placing mode, and space evenly
  (refer Figure 12, next slide). Then click on OK.
  This will place top-level pins evenly around the
  perimeter of the layout area.
• Save your design as pins.

43
Figure 12 The Place IO form
44
Placing Cells (Qplace)

• We are now ready to place cells onto our layout.
  Click on Place -gt Cells in the main window.
• In the Place Cells window, uncheck all the boxes,
  then click on OK. You may use timing or
  power-driven placement in the future, but for
  this tutorial we will use neither.
• Qplace will take a few minutes to complete.

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Figure 13 After Cell Placement
46
Viewing Layers (Silicon Ensemble)

• To view nets, special wires, pins, cell
  boundaries etc. while you are working on your
  design, make sure all the appropriate Vs
  (visible) fields are checked.

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Adding Filler Cells (Silicon Ensemble)

• 1. Click on Place -gt Filler Cells -gt Add Cells.
• 2. In the SROUTE Add Filler Cells form, type in
  FILL for Model, and fill for prefix.
• 3. Make sure ONLY the North and Flip South boxes
  are checked.
• 4. In the special pins section, add one entry for
  vdd and one entry for gnd (refer to Figure 16 on
  the next slide)

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Figure 16Add Filler Cells Form
49
Adding Filler Cells (Silicon Ensemble)

• 5. Click on OK.
• 6. This will add filler cells to your design.
  Filler cells provide n-well continuity for your
  standard cells.

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Figure 17 After Adding Filler Cells
51
Routing Power (Silicon Ensemble)

• 1. Click on Route -gt Route Power -gt Follow Pins.
• 2. In the Layers section of the Sroute Follow
  Pins form, set Width to 1.80.
• 3. Click on OK.

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Figure 18 Sroute Follow Pins Form
53
Figure 19 After SRoute Follow Pins
54
Wroute (Silicon Ensemble)

• 1. Click on Route -gt Wroute.
• 2. In the Wroute form, click on OK.
• Wroute will run. This will take a few minutes to
  complete.
• After this point, all the interconnect routing of
  the design has been done.

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Figure 20 After WRoute
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Viewing Different Layers in Silicon Ensemble

• You wont be able to see the interconnect metal
  layers in Figure 20 unless you enable the layer
  to be viewable.
• Click on View -gt Layers.
• In the Layer Visibility form, click on All
  Objects, then check all the layer check boxes.

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Display Options

• Silicon Ensemble allows you to customize the view
  window to display/not display certain parts of
  your design.
• In the main window, click on View -gt Display
  Options

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Display Options

• Notice the top part of the Display Option form
  allows you to select On, Here, Big, Small etc
  for the Level. By choosing a level here and
  clicking on the checkboxes, the selection for
  that particular checkbox will rotate between
  OFF and the level you chose.
• For example, select Small for the level. Now,
  click once on the Cells checkbox in the Objects
  section.
• If the checkbox was originally set to On, it will
  switch to Off after the first time you click it.
  Click on it again to set it to Small.
• Click on Apply.

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Display Options

• Your cell boundaries will now only be visible
  when you are zooming into a smaller portion of
  the design.
• If you click on the Fit button in the main
  window, you will not see the cell boundaries any
  more.
• Try zooming into a small area of the design. The
  cell boundaries will be visible again.

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Display Options

• The following explains the different levels
• - On visible at any level.
• - Here visible at level that is currently
  displayed in the main window.
• - Big, medium, small visible at big, medium or
  small levels respectively.
• - Off not visible at any level.

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Checking Pin Names

• You can easily check to see the names of the
  routed pins in the standard cells using the
  Display Options form.
• In the Names section of the Display Options form,
  set Pins to On, or Small.
• Click on the Apply button. The pin names will now
  be visible.

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The Find Form

• You can find cells, nets and pins etc. with the
  Find form. Click on Edit -gt Find to access the
  Find form.
• On the Find form, set Type to Net.
• Type msb_dp for the Name.
• Set the background dimmer to 70, then click on
  the Hilight button.
• The display will be dimmed, while the msb_dp net
  will be highlighted in the color selected in the
  Find form.

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The Find Form

• You can also give partial names, e.g. msb
  instead of msb_dp. If you click on the Show List
  checkbox, you will see a list of matching names.
• Type _csb for the net name, click on Show List,
  then click on Find. You should see a list of net
  names starting with _csb.

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The Find Form

• You can now click on each individual entry in the
  list, and highlight the particular net, or select
  it.
• The Find form, together with the Display Options
  form, provide a convenient way of debugging your
  overall routed design.

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Checking for Violations

• Violations will appear as X marks on your
  design. Be sure that there are no violations
  created during the routing.
• Silicon Ensemble will tell you the number of
  violations created during Wroute (Refer to Figure
  21, on the next slide). If there are any
  violations, be sure to fix them before moving on.
  You should not get any violations for this
  exercise.

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Figure 21 Total Number of Violations Reported by
Silicon Ensemble
68
Export to DEF Format (Silicon Ensemble)

• 1. Click on File -gt Export -gt DEF.
• 2. Type ../def_files/topchip_nopads_wrouted.def
  for the DEF file name.
• 3. Make sure the All checkbox is checked.
• 4. Click on OK.
• This will create the DEF file cadence/dp_se/def_fi
  les/topchip_nopads_wrouted.def.

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Running SEDSM in Script Mode

• When using SEDSM in interactive mode (like we
  just did), SEDSM will echo back your commands in
  the command-line window.
• If you enter these commands into a text file, you
  can run SEDSM in script mode. To run SEDSM in
  script mode, type the following in the
  cadence/dp_se/run directory
• sedsm b gdansi EXECUTE script.mac
• where script.mac is the name of your script file.

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Running SEDSM in Script Mode

• The cadence/dp_se/run directory has a script file
  called topchip_nopads_se.mac which will
  essentially perform all the procedures we did in
  interactive mode, from importing the LEF file to
  exporting the topchip_nopads_wrouted.def file.
• To execute the script file, go the the
  cadence/dp_se/run directory, and type
• sedsm b gdansi EXECUTE topchip_nopads_se.mac
  

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Re-running SEDSM after a Crash

• If Silicon Ensemble crashes while you are running
  it, you need to delete all the .dtp files in the
  cadence/dp_se/run directory before you run it
  again. The .dtp files are the lock files for
  Silicon Ensemble

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Cadence ICFB

• Cadence ICFB is the last CAD tool in this design
  flow. In ICFB, our design can be exported into a
  HSpice netlist, a Verilog netlist, or GDSII / CIF
  formats, among others.
• Cadence ICFB is potentially the most powerful CAD
  tool among the tools in this design flow, but it
  is also the most complex.

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Starting ICFB

• If youve previously used Silicon Ensemble in
  your current xterm window, launch a new xterm
  window.
• Change to the cadence/dfII directory.
• Type swsetup cadence-ncsu.
• Type icfb to launch ICFB.
• You should see three windows pop up the ICFB
  Command Interpreter Window (CIW), the Library
  Manager window, and another windows telling you
  about the changes for the latest version of ICFB.
  Close the third window.

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Importing DEF into ICFB

• In the CIW, click on File -gt Import -gt DEF.
• Enter tutorial for Library Name,
  topchip_nopads for Cell Name, and autoRouted
  for View Name.
• Enter ../dp_se/def_files/topchip_nopads_wrouted.d
  ef for DEF File Name.
• Make sure Silicon Ensemble is checked.
• Refer to Figure 22 (next slide) for all other
  options in the form.
• Click on OK. You will see some warning messages
  (about not being able to find site Core and site
  Double core). Ignore these messages.

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Figure 22 Import DEF Form
76
Figure 23 topchip_nopads autoRouted view
77
Importing DEF into ICFB

• Open the autoRouted view of topchip_nopads.
• In the autoRouted view, before you do anything,
  click on Design -gt Save. This ensures that if
  anything goes wrong, you can always come back to
  the autoRouted view.
• Click on Tools -gt Layout. This changes the tool
  from abstract-editing mode to layout-editing mode.

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Importing DEF into ICFB

• Click on Edit -gt Search
• In the Search form, search for inst in current
  cellview, with view name abstract. Replace with
  view name -gt layout. (Refer to Figure 24, next
  slide, click on add criteria then choose view
  name criteria)
• Click on Apply, then Replace All.
• Close the search form, then click on Design -gt
  Save as
• Save the design in the same library and cell, but
  change the view to layout.
• When you close the editing window, you will be
  asked if you want to save changes for the
  autoRouted view. Do not save any changes here or
  the autoRouted view will be over-written.

79
Figure 24 Search Form
80
Viewing Layers in ICFB

• Whenever in ICFBs layout editor, you can press
  shift-f to increase the number of layers viewed,
  or ctrl-f to decrease the number of layers
  viewed.
• For example, if you press shift-f while viewing
  the topchip_nopads layout, you will be able to
  see the metal, poly, active etc. layers of the
  individual standard cells. If you press ctrl-f,
  you will only be able to see the boundaries of
  the individual standard cells.

81
Figure 25 topchip_nopads layout view
82
Extracting a Verilog Netlist

• We need to extract a Verilog netlist out of our
  placed-and-routed design to verify that the
  place-and-route tools did their jobs without
  errors.
• This Verilog netlist will be simulated using
  Modelsim to verify for correct functionality.

83
Extracting a Verilog Netlist

• Before starting this section, change to the
  directory /ccs/issl/micro/users/tan/tutorials/desi
  gn_flow/cadence/dfII.
• Then, type
• rm rf topchip_nopads.verilog
• This will clear the Verilog netlister work
  directory.

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Extracting a Verilog Netlist

• First, we need to create an extracted view of our
  design. Open the layout view of topchip_nopads.
• Change the editing tool to layout editing by
  clicking on Tools -gt Layout.
• Click on Verify -gt Extract
• Make sure the macro cell box is checked. (Refer
  Figure 26, next slide)
• Click on OK.
• The extraction process will take a few minutes to
  complete.

85
Figure 26 The Extractor Form
86
Extracting a Verilog Netlist

• Click on Tools -gt Verilog-XL. You should see a
  new form called Setup Environment pop up on your
  screen.
• Enter topchip_nopads.verilog for the simulation
  run directory.
• Simulate the design in
• Library tutorial
• Cell topchip_nopads
• View extracted
• 10. Click on OK. (sample form is on next slide)

87
Figure 27 Setup Environment Form
88
Extracting a Verilog Netlist

• You will see a warning message as shown below.
  Ignore this warning message, since we are not
  going to simulate our design using Cadence. We
  are only going to use ICFB to extract a Verilog
  netlist.

89
Extracting a Verilog Netlist

• The Verilog-XL Integration window will now pop
  up. Click on Setup -gt Netlist
• The Verilog Netlisting Options form will pop up.
  Click on the More gtgt button. This will enable you
  to see all the options for this form.
• For the Netlist These Views field, enter
  behavioral functional symbol verilog.
• For the Stop Netlisting at Views field, enter
  behavioral functional symbol.
• Enter vdd and gnd for Global Power Nets and
  Global Ground Nets, respectively.
• Make sure the netlist explicitly box is checked.
  Then, Click on OK.

90
Figure 28 Verilog Netlisting Options Form
91
Extracting a Verilog Netlist

• Back in the Verilog-XL Integration window, click
  on Simulation -gt Start Interactive.
• The first time you run the verilog netlist
  extraction, you will get two errors regarding
  inherited nets for every instance you have in
  your design (on the order of a few thousand
  errors for our design). Ignore these errors -
  they are internal errors and should be fixed in
  the latest version of ICFB. Click on Simulation
  -gt Start Interactive again you will not get
  these errors the second time.

92
Extracting a Verilog Netlist

• 20. Ignore the warning shown below (click on OK).
  We can ignore this warning because we are not
  going to run Verilog simulation in ICFB.

93
Extracting a Verilog Netlist

• 21. A text file called verilog.inpfiles, located
  in the netlister work directory
  (cadence/icfb/topchip_nopads.verilog) is created.
  This file tells of the location of the Verilog
  netlists generated.
• 22. Using a text editor (pico, VI etc.), view the
  file verilog.inpfiles.
• 23. The text file will tell you the location of
  the top-level Verilog netlist it is going to be
  in ihnl/cds?/netlist, where ? will be a number.

94
Extracting a Verilog Netlist

• 24. Copy the netlist file from cadence/dfII/topchi
  p_nopads.verilog/ihnl/cds?, to cadence/dfII/gate.
• In the directory /cadence/dfII/gate, rename the
  netlist file to topchip_nopads_se.v.
• Use a text editor to view your verilog netlist.
  If the top-level module of topchip_nopads_se.v is
  not topchip_nopads, edit it to that name.
• 27. The next section of this tutorial will
  demonstrate how to simulate this Verilog netlist
  using Modelsim. However, before we go into that,
  lets discuss some other issues regarding ICFB.

95
Extracting a Hspice Netlist

• The procedure for extracting a Hspice netlist is
  similar to that of extracting a Verilog netlist,
  up to the Extractor form. There is only one
  difference for the Extractor form
• In the Extractor form, select Flat for Extract
  Method instead of Macro Cell.

96
Extracting a Hspice Netlist

• After running the Extractor form, follow the
  instructions below to generate a HSPICE netlist
• Click on Tools -gt Simulation -gt Other. You should
  see a new menu item - Simulation appear on your
  menu bar.
• 2. Click on Simulation -gt Initialize.
• 3. Enter topchip_nopads.hspice for the
  simulation run directory.
• 4. Click on OK.
• 5. Another Initialize Environment form should
  pop-up. This one has the full set of options to
  choose from.

97
Extracting a Hspice Netlist

• In the Initialize Environment form, choose hspice
  for the simulator name.
• Enter Tutorial for Library Name,
  topchip_nopads for Cell Name, and extracted
  for View Name.

98
Figure 29 Initialize Environment Form
99
Extracting a Hspice Netlist

• Go back to the Layout editing window, and click
  on Simulation -gt Options
• Make sure the Use Hierarchical Netlister and
  Re-netlist Entire Design boxes are checked, and
  the others are left unchecked.

100
Extracting a Hspice Netlist

• Go back to the Layout editing window, and click
  on Simulation -gt Netlist/Simulate
• Make sure that the netlist box is checked, and
  the simulate box is not. Also, check the Run in
  background box.
• The remaining information should be already
  filled in correctly for you. Make sure they match
  up to that shown in Figure 30. (next slide)

101
Figure 30 Netlist and Simulate Form
102
Extracting a Hspice Netlist

• Click on OK. Wait for a minute or so as ICFB
  works in the background to generate the Verilog
  netlist.
• A message telling you that the netlister has
  succeeded should pop up after a minute or so.
• The HSPICE netlist will be located in the
  directory that you specified as the run directory
  (for our case, cadence/dfII/topchip_nopads.hspice)
  , with the filename netlist.

103
Verilog or Hspice?

• For our case, Verilog is a more practical choice.
  
• Verilog is a switch-level language, which means
  it does not model any parasitics of the design.
  This makes simulation much faster than Hspice,
  which models the parasitics of the system.
• Since we started out with a VHDL file, we can
  assume that most of our designs will be
  relatively complex (e.g. having more than a few
  thousand transistors). Hspice simulation for
  designs of this scale is too time consuming.

104
Verilog or Hspice?

• For example, if we were to simulate our
  topchip_nopads design using Hspice for 150 us, it
  would take more than 24 hours to simulate.
  Verilog simulation using Modelsim takes less than
  1 second.
• Conclusion Hspice is great for detailed
  simulations (especially for analog systems), but
  for complex, purely digital systems, Verilog
  simulation is much more practical.
• Other simulators such as IRSim fall somewhere in
  between Verilog and Hspice simulators.

105
DRC Verification (ICFB)

• DRC (Design Rule Check) verification checks for
  design rule violations. The NCSU Cadence Design
  Kit comes with a decent (but by no means perfect)
  DRC checker.
• The NCSU kit DRC checker will flag certain metal
  constructs that should not be flagged as errors.
  Refer to the next slide for a more detailed
  explanation.

106
DRC Verification (ICFB)
Metal1 shapes

• The NCSU kit DRC checker will flag these as
  errors if the spacing is less than the minimum
  spacing for that metal layer, even though it
  should not matter because they all belong to the
  same net.

107
DRC Verification (ICFB)

• Open the topchip_nopads layout using the layout
  editor.
• Click on Verify -gt DRC
• Check Flat for checking method, and Full for
  checking limit.
• Click OK.
• DRC will run (this will take a few minutes), and
  subsequently return around a thousand false metal
  spacing errors.

108
Figure 31 DRC Form
109
Checking for Short Circuits between VDD and GND

• The easiest way to make your layout fail, is to
  have accidental shorts between VDD and GND.
• Shorts between VDD and GND can easily occur
  during manual layout procedures (e.g. when
  connecting the VDD and GND pads to the supply
  rings).
• Verilog extraction will not detect shorts between
  VDD and GND, because our Verilog simulating
  method ignores the VDD and GND nets.
• Therefore, it is essential to perform a quick
  check to make sure VDD and GND are not shorted.

110
Checking for Short Circuits between VDD and GND

• A simple way to perform this check is to open the
  extracted view of the layout. In the Library
  Manager window, open with extracted view of
  topchip_nopads.
• Now, click on the VDD (or GND) ring. If you
  clicked on the VDD ring, you should see the VDD
  ring, and the VDD rails highlighted. The same
  goes for the GND ring.
• If you see both rings highlighted when you click
  on either ring, then a there is a short from VDD
  to GND in your layout that must be fixed.

111
Exporting to CIF

• Most industrial foundries use a standard design
  transfer file format to send or receive design
  files. CIF is one such format.
• To export to CIF, click on File -gt Export -gt
  CIF
• Enter . for the run directory, tutorial for
  the library name, topchip_nopads for the cell
  name, and layout for the view name.

112
Exporting to CIF

• Enter cif_files/topchip_nopads.cif for the
  output file.
• Check the CIF DB box.
• Click on OK. This will generate a CIF file called
  topchip_nopads.cif in the cadence/dfII/cif_files
  directory.
• You will get some warnings (view the PIPO.LOG
  file) because not all layers in ICFB are
  translated into the CIF file. This is OK.

113
Figure 32 CIF Out Form
114
Modelsim

• The final step in our design flow is to simulate
  our ICFB-generated Verilog netlist using
  Modelsim.
• If the place-and-route procedures were
  successful, we should get the same results for
  this simulation as the simulation we ran with our
  Synopsys-generated Verilog netlist.

115
Modelsim

• There should be the following Verilog files in
  the cadence/dfII/gate directory
• topchip_nopads_se.v, which we just created,
• tb_topchip_nopads_se.v, the testbench file for
  the file above.

116
Modelsim

• Change to the qhsim directory.
• Type swsetup modelsim.
• 3. Type qvlcom ../cadence/dfII/gate/libcells_icfb.
  v
• 4. Type qvlcom ../cadence/dfII/gate/topchip_nopads
  _se.v
• 5. Type qvlcom ../cadence/dfII/gate/tb_topchip_nop
  ads_se.v

117
Modelsim

• Type qhsim tb_topchip_nopads . This will invoke
  Qhsim to simulate the testbench.
• There is a .do file in the qhsim directory that
  displays the signals and wave windows, adds all
  the top level signals into the wave window, and
  runs the simulation for 150 us. Activate the
  script by typing do tb_topchip_nopads.do in the
  command window. If you open up that .do file you
  will find that it contains the same commands that
  you would type in the command window to achieve
  the same results.

118
Modelsim

• Verify that the results for this simulation match
  that of the first Verilog simulation in this
  tutorial, by looking at the wave window.

119
Figure 33 Simulation Results Waveform