CSCE 612: VLSI System Design

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CSCE 612 VLSI System Design

• Instructor Jason D. Bakos

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Elements
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Semiconductors

• Silicon is a group IV element (4 valence
  electrons, shells 2, 8, 18, )
• Forms covalent bonds with four neighbor atoms
  (cubic crystal lattice)
• Si is a poor conductor, but conduction
  characteristics may be altered
• Add impurities/dopants (replaces silicon atom in
  lattice)
• Makes a better conductor
• Group V element (phosphorus/arsenic) gt 5 valence
  electrons
• Leaves an electron free gt n-type semiconductor
  (electrons, negative carriers)
• Group III element (boron) gt 3 valence electrons
• Borrows an electron from neighbor gt p-type
  semiconductor (holes, positive carriers)

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P-N junction
drift
forward bias
reverse bias
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MOSFETs

• Diodes not very useful for building logic
• Metal-oxide-semiconductor structures built onto
  substrate
• Diffusion Inject dopants into substrate
• Oxidation Form layer of SiO2 (glass)
• Deposition and etching Add aluminum/copper wires

negative charge (rel. to body) (GND)
positive charge (Vdd)
PFET/NFET
PMOS/PFET
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current
current
channel shorter length, faster transistor (dist.
for electrons)
body/bulk GROUND
body/bulk HIGH
(S/D to body is reverse-biased)
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FETs as Switches

• NFETs and PFETs can act as switches

CMOS logic
bulk node not shown
pull-up OFF pull-up ON
pull-down OFF Z (floating) 1
pull-down ON 0 smokin!
CMOS assuming PU and PN network are perfect
switches and switch simultanously, no current
flow and no power consumption!
and structure
or structure
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Logic Gates

• NMOS devices (positive logic) form pull-down
  network
• PMOS devices (negative logic) form pull-up
  network
• Implication CMOS transistor-level logic gates
  implement functions where may the inputs are
  inverted (inverting gates)
• Add inverter at inputs/outputs to create
  non-inverting gate

inv
NOR2
NAND2
NAND3
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Compound Gates

• Combine parallel and series structures to form
  compound gates
• Example
• Use DeMorgans law to determine complement
  (pull-down network)

C
A
B
D
Y
C
A
B
D
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Pass Transistors/Transmission Gates

• NMOS passes strong 0 (pull-down)
• PMOS passes strong 1 (pull-up)

Pass transistor
Transmission gate
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Tristates
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Multiplexer
Transmission gate multiplexer
Inverting multiplexer
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Multiplexer
4-input multiplexer
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Latches
Positive level-sensitive latch
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Latches
Positive edge-sensitive latch
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IC Fabrication

• Inverter cross-section

field oxide
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IC Fabrication

• Inverter cross-section with well and substrate
  contacts

(ohmic contact)
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IC Fabrication

• Chips are fabricated using set of masks
• Photolithography
• Inverter uses 6 layers
• n-well, poly, n diffusion, p diffusion,
  contact, metal

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IC Fabrication
Furnace used to oxidize (900-1200 C)
Mask exposes photoresist to light, allowing
removal
HF acid etch
piranha acid etch
diffusion (gas) or ion implantation (electric
field)
HF acid etch
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IC Fabrication
Heavy doped poly is grown with gas in furnace
(chemical vapor deposition)
Masked used to pattern poly
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IC Fabrication
Metal is sputtered (with vapor) and plasma etched
from mask
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Layout Design Rules

• Design rules define ranges for features
• Examples
• min. wire widths to avoid breaks
• min. spacings to avoid shorts
• minimum overlaps to ensure complete overlaps
• Measured in microns
• Required for resolution/tolerances of masks
• Fabrication processes defined by minimum channel
  width
• Also minimum width of poly traces
• Defines how fast a fabrication process is
• Lambda-based (scalable CMOS) design rules define
  scalable rules based on l (which is half of the
  minimum channel length)
• classes of MOSIS SCMOS rules SUBMICRON, DEEP
  SUBMICRON

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Layout Design Rules
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Layout Design Rules

• Transistor dimensions are in W/L ratio
• NFETs are usually twice the width
• PFETs are usually twice the width of NFETs
• Holes move more slowly than electrons (must be
  wider to deliver same current)

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Layout
3-input NAND
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Design Flow

• Design flow is a sequence of steps for design and
  verification
• In this course
• Describe behaviors with VHDL/Verilog code
• Simulate behavioral designs
• Synthesize behaviors into cell-level netlists
• Simulate netlists with cell-delay models
• Place-and-route netlists into a physical design
• Simulate netlists with cell-delay models and
  wire-delay models
• Need to define a cell library
• Function
• Electrical characteristics of each cell
• Layout

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Cell Library (Snap Together)
Layout