SPD ASIC design status'

1
SPD ASIC design status.

• Present Requirements.
• The 3V3 prototype.
• Preliminary test results.
• Key points to be analysed.
• Future work.

S. Bota, A. Diéguez, D. Gascón - October 2002
Barcelona
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I. Requirements (Energy measurement)
Energy deposition in a SPD cell (electrons and
photons).

• Energy deposition

• Random signal shape (20-30 phe/MIP)
• Shaping methods discarded

Single event MIP signal
Integrate
BW?100 MHz
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I. Requirements (Timing)
Average MIP signal

• Only about 80 of signal in 25 ns
• No dead time on integration

?d ?12 ns

• Dual channel synchronous system
• Pile-up correction

Normalized integral of Cosmic ray signals in main
and secondary period
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I. Requirements (Other)

• PMT gain limited by aging (DC current) ?
  100fC/MIP in central cells (HV650V).
• Resolution ? 0.05 MIP (ltlt resolution given by
  photostatistics).
• 5-10 MIP range to perform tail correction.
• Bandwidth gt 100MHz.
• Linearity error lt 5.
• Robust to temperature variations (band gap
  reference).
• Small cavity ? Power consumption lt 1W.

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II. The 3V3 prototype
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II. The 3V3 prototype (Input stage Preamplifier)
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II. The 3V3 prototype (Input stage Integrator)
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II. The 3V3 prototype (Input stage OpAmp)
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II. The 3V3 prototype (Input stage Noise and
Offset)
Transfer function of a system that integrates for
?T?

• Noise

• Offset

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II. The 3V3 prototype (Pile-up compensation
variable Gm)
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II. The 3V3 prototype (Pile-up compensation
Track Hold)
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II. The 3V3 prototype (Comparison input stage)
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II. The 3V3 prototype (Comparison latched
comparator)
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II. The 3V3 prototype (DAC)
7 bits floating DAC 1b for sign 6b for
modulus R-2R architecture
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III. Preliminary Tests Results

• PRELIMINARY RESULTS (automatic set up in
  progress...)
• Supply voltage ?1.65 V
• Consumption 25 mA (19 mA channel 6 mA for
  buffers).
• Pile-up correction control VbiasH1.65V
  VbiasL1.45V.
• Threshold dispersion (OZE at integrator output)
  65 mV r.m.s (for 10 samples) .

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III. Preliminary Tests Results

• Noise lt 2 mV r.m.s
• Synchronous noise effects have been observed
• Systematic test under different conditions
  (Threshold input, Pile-up control ....) when
  automatic set-up will be ready.

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III. Preliminary Tests Results

• Gain is about 3 times the gain of RUN2-3.
• Range for signal path is gt?1V (range for
  compensation to be studied).

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III. Preliminary Tests Results

• Linearity error of the generator has been
  measured calibration is needed.

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IV. Key points to be analysed

• Confirmation of offset measurements (20 chips
  will be packaged).
• Study of pick-up interference coming from
  switching on offset and noise.
• Sensitive points signal input, threshold input,
  pile-up compensation control...
• Dependence on board design...
• Study of pile-up compensation linearity
  (Temperature!).
• Matching of compensation factor (same control for
  different channels).

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IV. Future work.

• Complete test of RUN4 (channel and individual
  blocks).
• Prepare radiation tests for beginning 2002
• EVOLUTION OF FRONT END
• 300fC/MIP? 100 fC/MIP??
• Study how to increase the gain (if needed) ?
  offset cancellation is needed.

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IV. Future work.

• If the gain is not increased do we need to
  cancel the offset?
• The dynamic range will not be decreased because
  we can use the positive quadrant.
• 3?offset lt 500mV (to use the linearest region) or
  even 3? lt 1V.
• The DAC has a range of 320mV for 5 mV resolution
  (LSB). Therefore