ASIC 121: Practical VHDL Digital Design for FPGAs

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ASIC 121 Practical VHDL Digital Design for FPGAs

• Tutorial 2
• October 4, 2006

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Contributions

• I have taken some of the slides in this tutorial
  from Jeff Wentworths ASIC 120

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Combination vs Sequential

• Combinational Logic
• Output only depends on input
• Examples AND, OR, MUX
• Sequential Logic
• Output depends on inputs and memory
• Examples State Machine, Counter

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Memory

• Two popular ways of implementing memory
• Synchronous memory (most popular)
• Uses Flip Flops with a Clock signal
• Asynchronous memory
• Uses Latches
• Much more difficult to design with

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Basic Feedback Element SR latch
S R Q Qnext
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 N/A
1 1 1 N/A
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D Flip-Flop or Register
D Clk Q Qnext
0 0 0 0
0 0 1 1
1 0 0 0
1 0 1 1
0 0?1 0 0
0 0?1 1 0
1 0?1 0 1
1 0?1 1 1
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ASIC 120

• Read through the ASIC 120 Tutorial 2
• Gives a good explanation of state machines and
  basic VHDL

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Independent Tasks

• All students should have evaluation copies of
  Modelsim and Quartus II, if not see Tutorial 1

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Quartus II Exercise

• This exercise builds on the one performed in
  Tutorial 1
• Open Quartus II, Select File-gtNew Project Wizard,
  Select a valid working directory (should be an
  empty folder)
• Name the project and entity full_adder
• Click next for all other menus
• Select File-gtNew. Select VHDL File

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Quartus II Exercise Cont

• Save the file as full_adder.vhd, with the
  contents
• library ieee
• use ieee.std_logic_1164.all
• entity full_adder is
• Port ( i_X, i_Y, i_Cin in STD_LOGIC
• o_FA_Sum, o_FA_Cout out STD_LOGIC
• )
• end full_adder
• architecture main of full_adder is
• Component half_adder
• Port ( i_A, i_B in STD_LOGIC
• o_Sum, o_Carry out STD_LOGIC
• )
• end Component
• signal carry_1, carry_2, sum_1 STD_LOGIC

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Quartus II Exercise Cont

• begin
• adder1 half_adder Port map(
• i_A gt i_X,
• i_B gt i_Y,
• o_Sum gt sum_1,
• o_Carry gt carry_1)
• adder2 half_adder Port map(
• i_A gt i_Cin,
• i_B gt sum_1,
• o_Sum gt o_FA_Sum,
• o_Carry gt carry_2)
• o_FA_Cout lt carry_1 or carry_2
• end main

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Quartus II Exercise Cont

• Go to Project-gtAdd Files and add the
  half_adder.vhd file from Tutorial 1
• You have now seen a hierarchical VHDL design with
  multiple files

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Quartus II Exercise Cont

• Select Processing-gtStart-gtAnalysis and Synthesis
• Make sure it completes successfully
• Next Step
• Read through the help file under simulation
• Try Simulating the design

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Exercise 2

• Full adders can be chained together into
  something called a ripple adder
• 3 bit adder (A B S)

A0
A1
A2
B0
B1
B2
Carry Out
Carry In
S0
S1
S2
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Exercise 2 Contd

• Create the architecture description for a 4 bit
  ripple adder to implement the entity
• library ieee
• use ieee.std_logic_1164.all
• entity ripple_adder is
• port (
• A in std_logic_vector(3 downto 0)
• B in std_logic_vector(3 downto 0)
• c_in in std_logic
• sum out std_logic_vector(3 downto 0)
• c_out out std_logic
• )
• end ripple_adder

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VHDL DFF (Flip Flop)

• library ieee
• use ieee.std_logic_1164.all
• entity DFF is
• port ( d, clk in STD_LOGIC
• q out STD_LOGIC
• )
• end DFF
• architecture main of DFF is
• begin
• process (clk)
• begin
• if (clk'event and clk '1') then
• q lt d
• end if
• end process