1'1 Cfunction

1
1.1 C-function
Flowchart
int fac_c(int x) int f if(x lt 0) f 0
else f 1 while(x gt 1)
f f x x--
return f
fac_c(5) calculates 154321120
int fac_c(int x)
else
N
x lt 0
Y
if
f 0
f 1
while
N
x gt 1
Y
f f x
x x-1
You find a flowchart tool in Word or
Powerpoint. Could be useful for lab reports.
return f
End
2
Main in C
Message to the linkerfac_asm() is an external
function (from an other file).
includeltstdio.hgtextern int fac_asm(int)int
fac_c(int)int main(void) int c_result,
asm_result int x while(1)
printf(Enter a number ) scanf(d,
x) c_result fac_c(x) asm_result
fac_asm(x) printf(C-result d\n,
c_result) printf(Asm-result
d\n,asm_result) return 0
3
Structure diagram?
In assembler, we are not interested in the
program structure, but in the program flow.
The structure diagram could be directly
translated into structured programming.
4
The Flowchart
The flowchart could be directly translated to
assembler code.
5
Nios II registers 015
Use as constant 0!
If you call a subroutine, save the contents of
the registers youve used on stack!
6
Nios II registers 1631
Points to the stack!
7
Register operations, R-type instructions
8
Program constants, I-type instructions
Some pseudoinstructionsmovi rB, IMMED ? addi
rB,r0,IMMED movia rB,label ? orhi
rB,r0,hiadj(label) addi
rB,r0,lo(label)
9
I-type, Branch
Pseudoinstruction blebranch if less than or
equal signed bge is the ble with register A and B
swapped!
10
Conditional operators of C
Compare two registers and branch relative if the
expression is true.
All C-language conditional operators have
assembly instructions (or pseudoinstructions).
11
Memory content, Load and Store
Store in memory stw r6, 100(rA)
12
The call and ret instructions
13
From Flowchart to assembler
14
Assembler
fac_asm has to be made known to other files
.global fac_asm.text Parameter in r4 (and if
needed in r5, r6, r7) Return value in r2 (and
r3 if long or double) we can use r2 and r3 for
calculations until return r8 r15 must be
saved by caller of a subfac_asm int r2
fac_asm(int r4 x), the function prototype r3
for constant 1if ble r4, r0, else if(x
gt 0) movi r3, 1 constant 1
mov r2,r3 f 1while ble r4,r3,
endsub while(xgt1) mul r2,r2,r4
f fx sub r4,r4,r3 x x - 1
br while else mov r2, r0
f 0endsub ret return
r2.end
15
2.1 Prioritized interrupts
16
2.2 Input/Output
R/W reverses the direction of the databuss. CS
Chip Select enables the chip
Connect a 8 register memory-mapped peripheral to
the CPU. The CPU has 8 bit address and data
busses. The peripheral should have
registeraddresses 0x100x17.
17
Decode - doorlock
How to open the doorlock?
Press 4 (d) and 8 (h) simultaneously but dont
press any other key!
18
Connections
0x10 00010.000 0x11 00010.001 0x12
00010.010 0x13 00010.011 0x14 00010.100
0x15 00010.101 0x16 00010.1100x17
00010.111
19
Why memory cache?
20
3.1 Memory system
The memory is Byte-organized, but we could draw
it as if it was organized in Memory-lines with
the same size as the Cache-line.
Direct addressmapping Memory-line i ?
Cache-line j i K
21
Mapping of memory address
Memory 4kB 4210 212 Bytes. Memory address
mmmmmmmmmmmm
Cache 8 Word, 832 Bytes. Cache-line 2 Word, 24
Byte. Cache-addressll.w.bb
Memory Cache mappingmmmmmmm.mm.m.mmttttttt.ll
.w.bb Adress in Cache is irrespective of tag-bits!
Our example Data-adresses are acessed four
times in this order0x010, 0x1FC, 0x168, 0x008,
0x014, 0x1F8, 0x00C
22
Memory and Cache
Data is acessed from three different locations,
but they will map to the same lines in the cache!
23
Direct mapped Cache
24
Program execution
Data-adresses are acessed four times in this
order0x010, 0x1FC, 0x168, 0x008, 0x014, 0x1F8,
0x00C
Cache access, line(tag) 2(0)?3(1)?1(2)?1(0)?2(0)
?3(1)?1(1)?2(0)?3(1)?1(2)?1(0)?2(0)?3(1)?1(1)?
2(0)?3(1)?1(2)?1(0)?2(0)?3(1)?1(1)?
2(0)?3(1)?1(2)?1(0)?2(0)?3(1)?1(1)
CCCMHHMHHMMHHMHHMMHHMHHMMHHM
ColdMiss line entry to a previously unused
cache memory (This counts as
a Miss) Miss the previous line entry was from
an other location (tag) Hit the previous line
entry was from the same location (tag)
25
2-way set associative cache
Memory address mmmmmmmm.m.m.mm Address mapping
tttttttt.l.w.bb OBSERVE! The set number is not
included in the address map. Logic circuits
within the associtive cache takes care of the set
number and connects the CPU with the correct set.
26
Example of how an associative cache can boost
performance
Memory 0x010 Tag 0x01 Cache 0x00b0.0.00Memory
0x1FC Tag 0x1F Cache 0xC0b1.1.00Memory
0x168 Tag 0x16 Cache 0x80b1.0.00Memory 0x008
Tag 0x00 Cache 0x80b1.0.00Memory 0x014 Tag
0x01 Cache 0x40b0.1.00 Memory 0x1F8 Tag 0x1F
Cache 0x80b1.0.00Memory 0x00C Tag 0x00
Cache 0xC0b1.1.00
27
Fewer conflict misses
Memory locations 0x010, 0x014 are stored in
cache-line 0 But there are two sets! Both can
be stored simultaneously. 0x1FC, 0x168, 0x008,
0x1F8, 0x00C are stored in cache-line 1, Two of
them could be stored simultaneously. You have to
consider the exchange policy in order to be able
to analyse this example in full detail.
Exchange policy FIFO, RANDOM, LRU
28
3.2 Hitrate and accesstime
a) tAVG 8 ns h ? h is hitrate.
b) tAVG 15 ns h ?
c) tAVG 6 ns h ?
29
Hitrate calculations
tAVG 8, 15, 6 ns