CS318 Project

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CS318 Project 3

• Interrupts

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Credits

• Google
• http//www.beyondlogic.org/interrupts/interupt.htm
  

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On a Interrupt Request

• Processor finishes current instruction
• Pushes stuff on stack
• Think of only EFLAGS and EIP for now
• Invokes appropriate Interrupt Service Routine
• iret pops stuff off of stack

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How many Interrupts ?

• 256 total
• Most of them software interrupts
• 15 hardware interrupts
• The Programmable Interrupt Controller (PIC)
  handles hardware interrupts

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Hardware Interrupts

• Two 8259 PIC IC chips
• Base addresses 0x20h and 0xA0h

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PIC
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Control logic
IRQ 0 is asserted
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Interrupt Mask Register (IMR)
Control logic
Check if IRQ is masked
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Interrupt Mask Register (IMR)
Interrupt Request Register (IRR)
Control logic
Hold in IRR until processed
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Interrupt Mask Register (IMR)
Interrupt Request Register (IRR)
Priority Resolver
Control logic
Send INT to processor
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After finishing current instruction, checks if
interrupts disabled in EFLAGS
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Interrupt Mask Register (IMR)
Interrupt Request Register (IRR)
Priority Resolver
Control logic
Processor replies with INTA
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Interrupt Mask Register (IMR)
Interrupt Request Register (IRR)
In Service Register (ISR)
Priority Resolver
Control logic
Store in ISR, reset bit in IRR
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Interrupt Mask Register (IMR)
Interrupt Request Register (IRR)
In Service Register (ISR)
Priority Resolver
Control logic
Processor asks for data
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Interrupt Mask Register (IMR)
Interrupt Request Register (IRR)
In Service Register (ISR)
Priority Resolver
Control logic
PIC supplies data
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Interrupt Mask Register (IMR)
Interrupt Request Register (IRR)
In Service Register (ISR)
Priority Resolver
Control logic
Processor sends EOI
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Interrupt Mask Register (IMR)
Interrupt Request Register (IRR)
In Service Register (ISR)
Priority Resolver
Control logic
PIC resets ISR
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Small matter of cascading PICs

• 2nd PIC at 0xA0 was a later addition
• Setup in master-slave configuration to preserve
  compatibility
• You dont need to worry about it

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IRQ 2 routed via IRQ9
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INT of PIC2 via IRQ2
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All interrupts from PIC2 routed via PIC1 to
processor
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EOI for interrupts from PIC2 must be sent to both
PICs
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The End

• Questions?

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