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The ATLAS LAr. Calibration board
N. Dumont-Dayot, G.Ionescu, N.Massol, G.Perrot,
P.Perrodo, I. Wingerter-Seez LAPP, France  C. de
La Taille, N. Seguin-Moreau, L. Serin LAL,
France  K. Jakobs, U. Schaefer, D. Schroff Mainz,
Germany
ATLAS
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Contents

• The Calibration board in the electronics chain.
• Requirements
• Principle.
• The digital part.
• Prototype with DMILL Asics.
• Pulse shape.
• DC, Pulse uniformity and linearity.
• Timing and jitters uniformity.
• Conclusion.

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The Calibration board in the electronics chain
Timing Trigger Control
FRONT END ELECTRONICS

DAC
Pulsers
Calibration Board (130 )
BACK END ELECTRONICS
DETECTOR
E ? ai (Si - PED) E ? ? bi (Si - PED) ?2
? (Si - PED - E gi) 2
ANALOG MEMORY (SCA)
DSP
12 Bits ADC
1600 Optical GLINK links
Shaper
Front End Board
Read Out Driver
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Requirements
Goal Inject a precision voltage pulse as close
as possible as the physics pulse. Outputs 128
analog channels. Rise time lt 1ns, decay time
around 400 ns . Dynamic range 16 bits (2 µA to
200mA) . Integral non linearity lt 0.1
. Uniformity between channels lt 0.25 . Timing
between physics and calibration pulse
1ns. Radiation hardness 100 Krad, 1013 Neutrons
(DMILL Asics). Run at a few kHz.
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Principle
Analog part simplified schematics
Pulser principle
I2 µA to 200mA
V100 µV to 5V
Room temperature
Liquid Argon
16 bits DAC
Voltage follower
Voltage to current conversion
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The digital part
Slow control through I2C bus. Enable desired
channels ASICs REG0-3 (32 bits output
registers). Load DAC value ASIC DAC REG (16
bits output register). Delay calibration
command ASICs Delay0-1 (0-25ns step
1ns). Synchronous commands through TTCrx. TTCrx
decoding ASIC TTC decode (calibration command).
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Prototype with DMILL Asics (Nov 2002)
8x8 Op Amps pulsers
Channels lt63-0gt
DAC
TTCrx
Channels lt127-64gt
Power connector
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Pulse shape
Study over the full DAC range (100µV-1V) on 1
channel. Rise time lt 2ns (small variation
with DAC). HF ringings at small DAC value
(inductance package). Parasitic Injected Charge
Small signal when DAC0. Due to pulser
Cgs parasitic capacitance. Equivalent to
DAC15µV at the max. of the signal. Dynamic
range of 60 000 (1V/ 15µV).
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DC uniformity
Study for a 10mV DAC value. Measurements of
the DC current of the 128 channels.
Instrument 16 bits multimeter. Before
Operational Amplifier Offset correction Mean
1973.5µA RMS 6.17 s 0.31 After
Operational Amplifier correction Mean
1970.8µA RMS 1.04 s 0.05 DAC
voltage well distributed all over the board.
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Pulse uniformity
Study after shaping (CRRC2 50 ns) for a 10mV DAC
value Instrument 12 bits ADC sampling the
signal at the peak. s 0.33. Pulse and DC
uniformity well correlated.
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DC pulse linearity
Measurements on 3 gains (1,10,100) DC linearity
in black. Pulse linearity in red. Both
linearity within 0.05. Dynamic and DC
performances at the same level.
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Timing uniformity
Study of the delay between channel0 and the
others Measurements for a 30mV DAC
value. Instrument scope (1GHz analog bandwidth,
16Gsa/s). 1.2ns dispersion inside Op Amp rows
(common calibration command to 8 Op.
Amp.). Small dispersion between rows
(calibration lines not exactly equalized in
lengths). This will be corrected in the next
prototype layout.
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Jitters study
Jitters between TTC clock (TTCvx) and calib.
pulse Instrument Scope (1GHz analog
bandwidth, 16Gsa/s). Histogram
recording. Scanning TTCrx fine delay (0-24 ns
step 104ps) jitters within 44-58 ps. Scanning
Delay ASIC coarse delay (0-24 ns step
1ns) jitters within 48-53 ps. Values below the
100ps expected.
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Conclusion

• Prototype built with DMILL Asics (November 2002).
• Electrical measurements (uniformity, linearity)
  done.
• Timing measurements (uniformity, jitters) done.
• Front End Crate prototype installation done
  (March 2003).
• Final prototype expected soon (October 2003).
• Production of 130 boards will start spring 2004.