Standard Cell Library Optimization for Leakage Reduction

1
Standard Cell Library Optimization for Leakage
Reduction
Saumil Shah Univ. of Michigan Puneet Gupta
Blaze-DFM, Inc. Andrew Kahng Blaze-DFM, Inc.
43rd Design Automation Conference San Francisco,
CA July 2006
2
Outline

• Introduction
• Description of cell-variants for library
  enhancement
• Variant generation algorithm
• Delay and leakage models
• Experimental flow
• Variant generation results
• Circuit optimization results
• Conclusions and future work

3
Introduction

• Leakage power extremely critical to parametric
  yield at 90 and 65nm nodes
• Leakage is highly susceptible to process
  variability
• Extremely sensitive to gate-length variations,
  random dopant fluctuations
• Leakage analysis and optimization is a key design
  challenge
• Multiple Vth processes are now standard
• Only 2 or 3 different Vths are feasible due to
  mask costs
• Precise control of process implants becomes more
  critical for accurate Vth adjustment
• Gate-length biasing is gaining traction due to
  larger availability of design choices, ease of
  manufacturing and lower cost

4
Prior Work

• Gate-Length Biasing proposed in Gupta et. al.
  DAC 04
• Small gate-length biases for leakage reduction
• Cell-level biasing
• No method proposed for assigning gate-lengths
  individually to different transistors
• Transistor-Level Vth assignment proposed in Gupta
  et. al. ISQED 05
• Runtime issues
• Exhaustive search method
• SPICE simulation based methodology
• Limited to threshold voltage

5
Outline

• Introduction
• Description of cell-variants for library
  enhancement
• Variant generation algorithm
• Delay and leakage models
• Experimental flow
• Variant generation results
• Circuit optimization results
• Conclusions and future work

6
Variant List

• Choice of variants influenced by design slack
  characteristics, technology constraints
• Asymmetric design slack characteristics can be
  exploited
• Allowed bias values are determined by the foundry
• Positively biased variants generated for leakage
  reduction
• Negatively biased variants generated for timing
  optimization
• Dominant variants reduce both leakage and power

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Asymmetric Variants

• Exploit inherent asymmetries in rise/fall slack
  distributions
• Positively biased rise variant (R_P) for leakage
  reduction
• Identify devices contributing significantly to
  rise transitions and avoid biasing them
• F_P variant is analogous
• Negatively biased rise variant (R_N) for timing
  optimization
• Identify devices contributing to rise transitions
  and apply negative biases on them
• F_N variant is analogous

8
Dominant Variants

• M3,M4,M5
• Only 1 delay dominant state, 11
• M3,M4
• Only 1 leakage dominant state
• M5
• 3 leakage dominant states
• Reduce bias of M3,M4 increase bias of M5, to
  maintain delay of 11 input state
• Reduce overall leakage without delay penalty!

Errata This table replaces Table 3 in the paper
9
Outline

• Introduction
• Description of cell-variants for library
  enhancement
• Variant generation algorithm
• Delay and leakage models
• Experimental flow
• Variant generation results
• Circuit optimization results
• Conclusions and future work

10
Variant Generation Algorithm

• Biasability equation and biasing algorithm shown
  here are specific to the generation of type A
  variants
• Similar algorithms are utilized for the
  generation of other variants
• The equation is slightly modified in the case of
  rise, fall and dominant variants
• Starting and exit conditions differ during the
  generation of different variants

• Biasability computation
• Basic biasability equation

• Algorithm generateTLB
• For all i, biasi minBias
• computeBiasability()
• x0
• Iterate
• xx1
• biasi xbiasabilityi
• Snap bias to grid
• computeDelayOverhead()
• If Delay overhead gt Delay Upperbound
• solution previous bias
• return solution
• else
• goTo Iterate

11
Outline

• Introduction
• Description of cell-variants for library
  enhancement
• Variant generation algorithm
• Delay and leakage models
• Experimental flow
• Variant generation results
• Circuit optimization results
• Conclusions and future work

12
Delay-leakage modeling

• Delay Model
• RC model
• Each stage is reduced to a RC structure
• Only dominant devices considered
• Both gate and junction capacitance considered
• Lookup table for Rs and Cs generated by SPICE
  pre-characterization
• Leakage Model
• Sum of leakage of dominant devices
• Only off devices that are not stacked are
  considered
• Lookup table for off currents of individual
  devices
• Delay and Leakage Dominant devices determined
  based on the state table
• Accurate for relative delay overheads, required
  by algorithm

13
Outline

• Introduction
• Description of cell-variants for library
  enhancement
• Variant generation algorithm
• Delay and leakage models
• Experimental flow
• Variant generation results
• Circuit optimization results
• Conclusions and future work

14
Experimental Flow

• Industrial 90nm process with BSIM 4.3 models
• Variant list pruning
• Cell-usage statisitics
• Topographical analysis
• Avoid variants with biases exclusively on
  low-leakage devices
• Process and Design Constraints
• Poly-poly minimum spacing
• Poly-contact minimum spacing

SPICE Models
Process and Design Constraints
Existing Library
TLB Utility
Modified Library
Optimized Netlist
Verilog Netlist
Optimizer

• Sensitivity-based optimizer
• Transition-dependent slack-aware sensitivity
  function
• All experiments carried out on 3 separate
  libraries
• CLB-only library
• TLB-only library
• CLBTLB library

15
Outline

• Introduction
• Description of cell-variants for library
  enhancement
• Variant generation algorithm
• Delay and leakage models
• Experimental flow
• Variant generation results
• Circuit optimization results
• Conclusions and future work

16
Biasing Results

• R and F variants are clearly advantageous in the
  presence of asymmetric rise and fall slacks
• Dominant variants have small improvements,
  however, both delay and leakage are strictly
  improving

• TLB Cells found to have better delay/leakage
  trade-off compared to to CLB cells

5.36 for A_P, 5.13 for C_P4 and 4.84 for C_P6
17
Outline

• Introduction
• Description of cell-variants for library
  enhancement
• Variant generation algorithm
• Delay and leakage models
• Experimental flow
• Variant generation results
• Circuit optimization results
• Conclusions and future work

18
Circuit Optimization Results Leakage Reduction

• Leakage improvements for TLB cells are found to
  be considerably better over CLB cells
• On average, 12 improvement over CLB optimized
  designs

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Circuit Optimization Results Leakage
Variability Reduction

• 39 variability reduction over CLB for test
  circuit

20
Outline

• Introduction
• Description of cell-variants for library
  enhancement
• Variant generation algorithm
• Delay and leakage models
• Experimental flow
• Variant generation results
• Circuit optimization results
• Conclusions and future work

21
Conclusions and Future Work

• Transistor-level gate-length biasing methodology
  proposed
• Sensitivity-based heuristic for assigning bias to
  each transistor based on delay-leakage tradeoff
• Up to 17 additional reduction in mean of leakage
  compared to CLB-optimized design
• Up to 39 reduction in variability of leakage
  compared to CLB-optimized design
• Future work
• Extension to include sequential cells
• Simultaneous Vth assignment and gate-length
  biasing
• Use of negatively biased variants for timing
  optimization and enhanced leakage optimization
• Improvement of delay-leakage modeling accuracy