Advanced Digital Circuits ECET 146 Week 5

1
Advanced Digital CircuitsECET 146Week 5

• Professor Iskandar Hack
• ET 221B, 481-5733
• hack_at_ipfw.edu

2
This Weeks Goals

• Introduction to the concept of Hierarchical
  Design Techniques
• Designing a circuit with multiple projects
• Designing an counter in VHDL

3
Hierarchical Design Techniques

• Also called Top-Down Design
• A design technique that allows a project to be
  broken into a series of smaller projects
• Each subdesign is developed and tested separately
  
• The overall design is then assembled using either
  Text Design Techniques or by connecting the
  subdesigns in the graphical editor (preferred
  method for this course)

4
Design a four-bit full adder using Hierarchal
Techniques

• Create a project for One-Bit Half Adder
• Enter Design
• Compile
• Create Default symbol
• simulate project HA
• Create a project for One-Bit Full adder
• Repeat steps from above
• Create a new project fourbitadd in Graphical
  Editor
• Insert a half adder and three full adders, and
  connect as done in ECET 11
• Simulate full design
• These circuits can be found on pages 236-238 in
  ECET 111 textbook

5
Enter Design for Half Adder
Half Adder
Simulation of HA
6
Remember steps from earlier lectures

• Enter the design using
• Input
• Output
• XOR
• AND2
• Name the pins
• Save file as ha.gdf
• Set project to current file
• Save and Compile (dont worry about set device or
  pins since were not going to build the subdesign
  in hardware)
• Draw Waveforms for Simulation and Simulate

7
Create Default Symbol

• This step creates a schematic symbol that can be
  used in other designs

8
Default Symbol for Half Adder
9
Full Adder

• Repeat process for the Full Adder that you did
  for the Half Adder

10
Change Top-Level prior to Simulation

• Before you can simulate FA, youll have to change
  the project top to the current file (note youll
  have to have the file open to do this).
• Recompile after changing the top level

11
Note about Simulation File

• Quartus requires that you the same name as the
  Project Name (in this case the first HA) as the
  name of the Simulation VWF for all simulations.
  Thus to simulate all other waveforms same the
  file with the name HA.wvf

12
Simulation for Full Adder
13
Default Symbol for Full Adder
14
Draw Four-Bit Adder

• Open Graphical Editor and add the symbols ha and
  4-fas and connect them as shown with inputs and
  outputs similar as shown on page 238 in Kleitz
• Note All files MUST be in the same directory on
  the drive!!!
• Do not put ha, fa and fourbitadder in different
  directories.

15
Fourbitadder drawing
16
Save, Compile, Define Device and Pins

• After drawing the fourbitadder save it as a new
  file (fourbitadder.bdf)
• Set as Top-Level Enity
• Compile
• Set Device as before to EPM74128SLC84-7
• Define input pins and output pins
• Recompile after making assignments!!!

17
Pin Assignments
18
Simulation

• Simulate as before (sample shown)

19
Simulate

• Save the file as fourbitadder.scf and simulate

Glitches because of propagation delays
20
Lab 4

• Implement an 8-Bit adder as discussed in this lab
• Simulate the design
• Do not Build the circuit, just turn copies of the
  HA, FA and eightbitadder GDF files and simulation