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Advanced Digital Circuits ECET 146 Week 11

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Almost always built from a array of rows and columns. Most use momentary close push-button switches ... Net Names and must. Be named to rip signals. From Bus. Lab 10 ... – PowerPoint PPT presentation

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Title: Advanced Digital Circuits ECET 146 Week 11


1
Advanced Digital CircuitsECET 146Week 11
  • Professor Iskandar Hack
  • ET 221G, 481-5733
  • hack_at_ipfw.edu

2
This Weeks Goals
  • Review of Keypads
  • Use of the Case Statement
  • Use of IF THEN ELSE
  • Use of ELSIF
  • Project using keypad with another FSM

3
Review to Keyboards
  • Almost always built from a array of rows and
    columns
  • Most use momentary close push-button switches
  • When a switch is closed this causes a short
    between one column and one row
  • Either the rows or columns are taken high (or low
    for an active low system) one at a time and the
    lines for the columns or rows are monitored for a
    high (or low if active low system)

4
An Example Keyboard
Column Lines are on Pins 5-8
Row Lines are on Pins 1-4
5
What happens when a button is Pressed
  • If the 6 button is pressed then there will be a
    short between the 2nd row (pin 2) and the 3rd
    column (pin 7)

6
Scan Function
  • The purpose of the scan function is to drive the
    input lines (well use the rows as the inputs in
    this example) with a high during each clock cycle

Then 2nd row
Then 3rd
Take the first row high
Last row
Repeat cycle
7
Scan Function Designed in AHDL (note in cut and
paste format)
SUBDESIGN scan ( clk, reset INPUT
scanlines3..0 OUTPUT ) VARIABLE ss
MACHINE OF BITS (scanlines3..0) WITH
STATES ( s0 B"0001", s1
B"0010", s2 B"0100", s3
B"1000") BEGIN ss.clk clk ss.reset
reset TABLE ss gt ss s0 gt
s1 s1 gt s2 s2 gt s3 s3 gt s0
END TABLE END
Note in this case Im assigning the Outputs for
each state in the declaration. Not always the
most best for optimization, But makes the design
a bit simpler.
8
Symbol for Scan Function
9
Decode Function
  • First of all it must look for a high on ANY of
    the four return lines (this are the rows in this
    example)
  • If any input is high then we know a key has been
    pressed.
  • Then we look at what scan line is high and what
    return line are high (note there will always a
    high scan line because of the way we designed the
    scan function) and decode what key has been
    pressed.
  • The decode function is unique for every keyboard
    and the way its used in the circuit for
    example if we chose to have the scan lines go to
    the columns and the return lines go to the rows
    we would have a different table for the decode
    function.
  • We will have two four bit inputs for this
    function scan and return. Well have a four bit
    output for the keycode and an one bit output for
    active keypress.

10
Decode Table Guidelines
  • First look at the keyboard layout and what keys
    are at each row/column position
  • For each position youll output that key value
    when that row/column position is high
  • You only have to include in the table the values
    for the row/columns of 1, 2, 4 and 8 since only
    one line can be high (were ignoring multiple key
    presses) at a time

11
Decode Table
3rd column has a value of 4 and 3nd row has a
value of 4
12
Decode Function AHDL (cut and paste format)
SUBDESIGN decode ( scan3..0, return3..0
input keycode3..0, keypress output )
BEGIN TABLE scan, return gt
keycode, keypress x, 0 gt 0, gnd
1, 1 gt 1, vcc 1, 2 gt 4, vcc 1, 4 gt
7, vcc 1, 8 gt 10, vcc 2, 1 gt 2, vcc
2, 2 gt 5, vcc 2, 4 gt 8, vcc 2, 8 gt
0, vcc 4, 1 gt 3, vcc 4, 2 gt 6, vcc
4, 4 gt 9, vcc 4, 8 gt 11, vcc 8, 1 gt
12, vcc 8, 2 gt 13, vcc 8, 4 gt 14, vcc
8, 8 gt 15, vcc END TABLE END
13
Symbol for Decode Function
14
Complete Keypad System
  • The complete system will have a scan function
    that will drive the columns (also go into the
    decode function) and the decode function
  • Of course youll need the keypad itself
  • One important point you will need to place
    pull-down resistors on the return lines.
  • Whenever there is no key pressed then the return
    lines are floating (neither high or low), thus we
    need to place a 1K resistor between the return
    lines and ground to ensure that when there no
    connection to VCC (through the scan lines)

15
Altera Keypad Project Keypad and pull-down
resistors are external from the Altera Part
Note the names of the nets and I/O
16
Symbol for Altera Keypad Project
17
Drawing of Connections between Altera and Keypad
Note Pulldown Resistors
18
Using a Keypad within a Larger Project
  • First you must design, simulate and test the
    keypad as done in Lab 8
  • Design the Main part of the project with keycode
    and keypress as inputs (note we didnt bring
    keypress out of the project in Lab 8, so you need
    to modify Lab 8 to bring it out.)
  • In all states that wait for a keypress, we will
    have the table loop back until keypress is equal
    to Vcc. (similar to what we did with te in
    timedelay)
  • Once a key is pressed then we look at the keycode
    to decide how our main FSM is to proceed.

19
Example Combination Lock
  • This is a simple 3-digit combination lock that
    waits for the right combination to be pressed.
  • Once the correct combination has been pressed
    then simply light an LED until another key is
    pressed.
  • Well use the combination of 123 for this
    example.
  • Note this simple lock has the combination encoded
    in hardware, as you work this in the lab think
    about how you might be able to change the
    combination.

20
State Diagram for our Lock
21
State Transition Table for Combination Lock
22
Problems with use of Table Command
  • The TABLE command in Alteras AHDL does not allow
    the use of ltgt or ! (not equal) thus the table
    would have to be very large to accommodate all of
    the possible incorrect keys.
  • Thus it is impractical (and could lead to a very
    large circuit) it attempt to use this method.
  • A better solution is to use a CASE statement
    which has a default clause.

23
Case Statement
  • The Case Statement lists the alternatives that
    may be activated depending on the value of the
    variable, group, or expression following the CASE
    keyword.

24
Examples of Case Statements
Combinational Logic for decoder
State Machine Logic
Mix of combinational And counter
25
IF Statement
  • Similar in syntax to C or any other programming
    language
  • Format is normally the word IF followed by a
    Boolean expression that is evaluated as TRUE or
    FALSE
  • If the expression is TRUE then the logic
    statements following implemented.
  • BE CAREFULL AHDL is a concurrent language ALL
    true if statements in a design are implemented in
    hardware simultaneously. This could cause some
    major problems if one IF-THEN-ELSE statement
    takes a signal high at the same time another
    statement attempts to take it low. My experience
    is that the software doesnt always find those
    types of errors.
  • Must end an IF THEN statement with the END IF
    statement

26
Examples of IF THEN Statements
Simple Boolean Logic
Within Case Statement To determine next state
27
ELSE Clause
  • It is optional for an IF THEN statement to have
    an ELSE clause
  • If there is an ELSE clause then the statements in
    ELSE clause if the Boolean expression is
    evaluated to be FALSE
  • The Statement is the equivalent to starting
    another IF THEN statement, however youll only
    need one END IF to end the IF structure

28
Examples Using ELSE (and ELSIF) Clause
29
Comments Regarding IF versus Case
  • The way that the software analyzes if/then/elsif
    type statements can cause Altera to create some
    very inefficient logic.
  • It is okay to use IF/THEN/ELSIF logic, but be
    careful not to nest more than 2 to 3 levels

30
Alteras Comments on Case vs. IF
Note that as we move down the IF/ELSIF structure
the Boolean Expression gets more complex.
31
Implementation of Combination Lock using Case
Statements and IF/THEN
32
Continue with Example Code
33
Full Design of Lock System
Bus name must match Net Names and must Be named
to rip signals From Bus
If you name a net (line) the same the
software Will connect them internally,
simplifying the drawing
34
Lab 10
  • Building on Lab 9 design a simple combination
    lock with the combination being the last 2 digits
    of each lab partner SSN (four digits altogether)
    the order doesnt matter
  • This lab must be built and demonstrated
  • There is also a complete lab report for this lab
    (incorporating Lab 9)

35
Keypad Data Sheet
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