Addressing Modes of Operands

1
Addressing Modes of Operands

• Provides the means ways to access various
  operands in an assembly language program.
• Supported by dedicated hardware components
  existing within the CPU as well as by the
  underlying Control unit i.e. Completely
  Architecture Dependent.
• Aides in implementing various High Level
  Language (HLL) Data Structures at Machine level
  thereby easing the jobs of compiler writers.

2
The Basic types of Operands

• The CPU Registers ( GPRs and /or other Special
  types of User Accessible Registers like Stack
  Pointer , Program Counter , FLAGS (Program Status
  Word PSW) etc.
• Some Immediate Operands or constants.
• Memory / Main Memory (usually RAM /RWM
  locations).
• Various peripheral Interface Registers ( normally
  accessible in Supervisor / Privileged mode).
• N.B i)CACHE Memory are NOT accessible by any
  instruction.
• ii) Storage lying on Secondary
  Memory Medias are accessible as Files through
  O.S.

3
The Basic Addressing Modes -1

• Register Direct / Register The L_Value of the
  Operand (Operand Address) happens to be some CPU
  Register specified explicitly in the instruction.
  Hence the Operand value (R_Value) will be the
  content of the specified Register.
• e.g. MOV r1,r2 gt
• The CPU Register r1 L_Value referred as r1
  ? The content of the CPU Register r2 R_Value of
  r2 referred as (r2)

4
The Register Addressing Modes (Contd.)

• 2. Implied Addressing Mode In some CPUs or in
  some Instructions one of the Register Operands
  may be implied i.e. not mentioned Explicitly in
  the instruction.
• e.g.
• (a) ADD r1,r2 gt r1 ? (r1) plus (r2)
• Here the destination / Result Operand is
  implied.
• (b) IMUL r1,r3 gt Signed Multiplication
• Reg. Pair r1r2 ? (r1) X (r2)
• Here the destination / Result Operand is
  implied.

5
The Basic Addressing Modes -2

• 2. The Immediate Mode Used exclusively for
  initializing CPU Registers and /or Memory
  Locations. In this case some constant values is
  directly specified in the assembly instruction as
  the Source Operand (R-Value).
• e.g .data Start of Data Segment
• ORG 02000 0000H Set Up Data
  Segment Offset
• A1 EQU 0000 0045H Symbolic
  Constant A1 define A1 OX 45
• B1 DD ? Uninitialized Word
  Size Memory Location B1
• C2 DD ? Uninitialized 32
  Bit Word Size Memory Location C2
• .text / .code Start of Code
  Segment
• ORG 0A000 0000H Set Up
  Code Segment Offset
• MVI r1, A1 CPU
  Register r1 ? Hex value 0000 0045
• STI B1, A1 Memory
  Location B1 ? Hex Value 45
• MVI r2, 0000 0056H
  CPU Register r2 ? 0000 0056 H
• STI C2, 07BH
  Memory Location C2 ? 0000 007B H

6
The Basic Addressing Modes -3

• 3. Memory Addressing Modes Presents the widest
  possible variations in the Addressing Modes. The
  more rich this addressing mode is , the better
  support it provides for implementation of High
  Level Languages Structured Data Types and / or
  Abstract Data Types (ADTs).

7
Commonly Supported Memory Addressing Modes - 1

• 1. Memory Direct / Direct Addressing Modes
• The type of addressing we have used so far in
  which the RAM / RWM memory location (Main Memory
  Location L_Value ) is specified either
  symbolically or by the offset
• e.g. .data Start
  of Data Segment
• ORG 0000
  67A9 H Set Up Data Segment Offset
• Location Symbol Directive R_Value
• (L_Value Data Segment Offset )
• A1 DD 0000
  0056H
• A1 is Having Location offset
  (L_Value) 0000 67A9 H
• Content of A1 (R_Value) 0000 0056 H
  
• .text / .code Start
  of Code Segment
• ORG 0000
  BD00 H Set Up Code Segment Offset
• LOAD r2, A1
  r2 ? Content of Mem A1 M(A1)
• LOAD r3, 0000
  67A9H r3 ? M(0000 67A9H)
• At this point CPU Register
  r3 CPU Register r2 0000 0056 Hex

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Commonly Supported Memory Addressing Modes - 2

• 2. Accessing Address Pointers (L. Value)
• Some modern day processors allows the address
  (L. Value) of a location to be used as operand
• e.g. Load effective Address In Pentium
• .data Start of Data Segment
• ORG 02030 AB87 H
• M DB 45H L_Value of M
  2030AB87 H
• .code Start of Code Segment
• ORG 0B000 AF00 H
• LEA r2, M
• CPU Register r2 (32 bit) ? The offset
  address of
• the Main Memory Location M here 2030
  AB87 H

9
Extended Memory Addressing

• Base Value stored in a register extended /
  appended / concatenated partially/fully by an
  Offset / Displacement.
• e.g.
• LOAD r1, _at_ (0020H) r2
• gt r1 ? M 0020 concatenated with
  (r2)
• if r2 in our sample Machine contains 0000 4000
  H
• Then we are referring to an address 0020 0000
  4000H
• This reduces no. of bits in the Operand address.

10
Indirect Addressing Modes

• In this case the Operand Address is specified
  in a round about way i.e. through some Address
  Pointer(s). Following two cases are worth
  Mentioning
• Register Indirect.
• Memory Indirect.

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Indirect Addressing Modes -2

Register Indirect Register points to the
operand location e.g. .data
ORG 0040 0030 H Set Up Offset Data Addr
A1 DD ? Un-initialized Variable
.code ORG 0A000 0000 H
LEA r0, A1 CPU Register r0
points to Location A1 ADD (r0), r2, r3
M(r0) ? (r2) PLUS (r3) M(r0) gt Content of
the location whose address is in register r0
i.e. which is pointed to by the register r0.
Here r0 contains 0040 0030 Hex Memory offset
0040 0030 Hex i.e. A1 ? (r2) PLUS (r3)
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Indirect Addressing Modes -3

• Memory Indirect Some Memory location acts as
  pointer to the operand location
• ltOP Codegt (ltPointer Location gt)
• e.g.
• STORE (A1), r2 gt M (M(A1)) ? (r2)
• M (A1) gt Content of the location whose
  address is A1 .
• M(M(A1)) gt Content of the location which is
  pointed to by the
• Memory Location A1
• Say Allocated Offset / Allocated L_Value of A1
  6000 0000Hex
• M(A1) i.e. M (6000 0000) 4000 8000 Hex
• Then this Instruction will cause M (4000 8000) ?
  (r2)

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Auto Increment , Auto Decrement Addressing Modes
1

• A subtle variation of Memory Addressing suitable
  to be used in accessing a Block of Elements in a
  Loop
• A few simple examples are given below
• (1) Memory Direct
• A DW 034E1 H
  Little Endian Convention
• A DB 0E1 H
• A1 DB 034 H
• B DB 046 H
  
• XCHG A, r1 Increment A
  by 1
• Swap
  M A with the contents of Register r1
• XCHG B,r1 Swap the contents
  of r1 with MB
• XCHG A1, r1 Swap r1 with M
  (A1)
• After executing this instruction M (A1)
  will be 46 Hex
• and M(B) will be 34 H

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Auto Increment , Auto Decrement Addressing Modes
Example - 2
2) Post Decrement Address specified as Register
Indirect MVI r2 , 0A12F 9010H r2
? A12F 9010 H STI (r2) - , 04D00 A000 H
M ((r2)) ? 4D H Memory Location
A12F 9010 ? 4D00 A000 H
Decrement r2 LOAD
r0 , (r2) r0 ? M (A12E 9009H)
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Auto Increment , Auto Decrement Addressing Modes
Example - 3

• 3) Memory Indirect
• .data
• ORG 0E000 0000 H
• A1 DD 0E000 0003 H A1 is a 32 Bit
  Variable with
• L_Value E000 0000H R_Value
  of A1 E000 0003 H
• B1 DW 0A239 H L_Value of B1
  E000 0004 H
• 
  R_Value of B1 A239 H
• LOAD r1 , (A1) Increment A1 by 1 it
  becomes E000 0004 H pointing
• to B1 then r1 ? M ( M (A1)) i.e. M
  (E000 0004) actually M(B1)
• r1 will now contain 0000 A239 H i.e.
  0000 M(B1)

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Relative Addressing Modes - 1

Mostly used as Branch Addressing ( Helps in
Eliminating the Need to Relocate Branch Addresses
) e.g. JNZ 5 H gt If the last
computation has not set the the ZERO
Flag then Jump to the Location
Obtained by Adding 5 Hex to the Current
Content of the Instruction Pointer
(IP) / Program Counter (PC)

17
Accessing Structured Data Types - 1

• 3. Accessing Array Elements
• Consider an array declaration in C
• int A1 10 // A 10 Element Integer Array
• int I 4
• A1 I 5 //
• Here A1 gt The Array Name / BASE Address
• I gt The Array Element Index .
  
• a) Array Element Size Memory Location Size
  1 Byte OR
• b) Array Element Size CPU Word Size 4 Bytes
  Here.
• In order to implement this in Assembly Level ,
  several modes may be existing.

18
1- D Array Access Basic Mechanism

• Specify the Base Value ( Either Explicitly or in
  a CPU Register ).
• Specify the Index Value in one of the following
  manners
• a) In an Index Register multiplied by a Scale
  Factor ( default Scale Factor 4 Bytes in our
  Machine).
• b) Explicitly as a Displacement Value.
• c) A combination of a) b).

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Accessing 1-D Array Elements - 1
a)INDEXED Base is explicitly specified while
index is available in an Index register
e.g. 2 operand case LOAD r1, Ar3
r1 ? Content of the Main Memory Location A
M(A) CPU Register r3s Content . Here A
represents the Symbolic BASE

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Accessing 1-D Array Elements - 2

• b)BASED Here Displacement / Index is
  explicitly specified while Base is stored in a
  register (base register)
• e.g. LOAD r1, r2 I gt
• r1 ? M (r2 PLUS M(I))
• where I gt Symbolic Index

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Accessing 1-D Array Elements - 3

• c)Based/Indexed Here both index and base are
  stored in separate registers
• e.g. LOAD r1, r2 r3 gt
• r1 ?
  M (r1 r3)

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1-D Array Access in Our Machine - 1

• Base Value as a Data address offset specified as
• a) An Explicit 16 bit Value e.g. 0A000 H.
• b) A Symbolic Value e.g.
• .data
• ORG 0A000 0000H
• A1 DD DUP (10) A Block of 10
  Words with
• A1 as start pointer.
• c) In a Register
• MVI r1 , 0A000 0000H
• Now r1 will contain A000 0000H which is
  treated as base.

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Indexing 1-D array in Our Machine

• a) In an Index Register .
• e.g. LOAD r4, r0x r2,n / r2 base
  r1
• Index (r2) X n where n 4 or Higher
  .
• n may be omitted assumed 4.
• r4 ? M (r1 PLUS r2 X n )
• b) Explicitly as a Displacement Value.
• e.g. LOAD r4, r1 ,40
• r4 ? M (r1 PLUS 40 )
• c) A combination of a) b).
• e.g. LOAD r4, r1 r2,4,40
• r4 ? M (r1 PLUS r2 X 4 PLUS 40 )