BWRC Retreat

1
BWRC Retreat

• Design of a 2-1 MASH Sigma-Delta ADC
• Bill Tsang, Yun Chiu, Borivoje Nikolic
• 01/12/2004
• Monterey,CA

2
Outline

• Motivation
• 2-1 MASH Sigma-Delta(??)Architecture and
  Implementation
• Layout
• Simulated Results
• Summary

3
Motivation
High precision ADC (14-bit)
S/H
S/D ADC
?n
fclk/n
Pipeline ADC
Vin
Dout
fclk

• Integrating slow, comparator offset
• Algorithmic, successive approximation high gain
  op-amp, precision capacitor matching
• Sigma-delta(??) no high precision analog
  circuits

4
?? ADC
fs/2M
conversion rate1/T

• DC input decimation filter needs time to settle.
• To decrease the settling time an alternative
  filter can be used.

Wider filter transition band gtshorter digital
filtergt shorter transient responsegthigher
conversion rate Side benefit attenuation of
inband quantization noise
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2-1 MASH ??

• Cancellation of quantization noise in digital
  domain
• Matching of ? limits the additional dynamic range
  
• Matching of ? is irrelevant(higher-order error)

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2-1 MASH ??

• Applying voltage scaling to reduce the integrator
  voltage swings
• Quantization noise level is equivalent to a 3rd
  order sigma-delta ADC
• Input referred electronic noise is increased

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Noise

• Noise/error source sampling, OTAs, finite OTA
  DC gain.
• All noise sources referred to the integrator input

where SN,ninput inferred noise at nth integrator
input

• Use the above equation to determine capacitor
  sizes

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Matching
For perfect ? matching

• M64, ?0.5
• SQNR100dB

• The resolution is primarily limited by electronic
  noise

9
Circuit Detail

• Switched-capacitor implementation
• 3 integrators, 2 comparators
• Bootstrapped switches in the first stage
• Non-overlapping clocks

Analog
Digital
10
Floor Plan
Signal flow
Floor plan of the ?? ADC

• Clocks routed from the left to the right
• Most important matching of relevant capacitors

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Layout (Integrator I)

• Need to match CsCfBA14f1

ACf BCs CDummies Unit element500fF

• Common centroid layout (process gradient)
• Dummies (proximity effect)
• Careful routing of signals (parasitic capacitance)

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Layout (Integrator I)

• 0.13?m CMOS
• Capacitor inter-digitated finger capacitor (CMOM)

Cs,Cf
Bootstrap switches
CMFB
CLoad
OTA
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Simulation Results

• Digital correction logic and decimation filter in
  Simulink
• Interested in time domain

Digital code
??
DC
14
Summary