"Test and Debug" subnetwork

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"Test and Debug"sub-network
EUROSOC Proposal
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Paradigm shifts

• Testing cost may represent up to 50 of the
  manufacturing cost of SoC
• Sky-rocketing complexities
• Decreasing pin/gate ratio
• Higher frequencies
• Decreasing product life cycles
• SoC Testing
• Hardware/software designs
• IP-based designs
• Increasing use of analog, mixed-signal and RF IPs
  

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Paradigm shifts (2)

• New defects due to technology evolution
• Core-based testing
• Test of programmable (HW/SW) systems
• Increase of temporary faults (transient and
  timing faults)

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Barriers to overcome

• Development of nanometer fault models
• ATPG, BIST for real defects
• Reduction of test execution time
• Power consumption during test
• Optimized Test Resource Partitioning strategies
• Obsolescence of Iddq testing
• Analog BIST
• Tolerance of temporary faults (Effects of cosmic
  radiation, SEU defects)
• DfD methodology

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"Test and Debug" sub-network

• Proposed Key Node
• Christian Landrault (LIRMM/University of
  Montpellier, France)
• Erik-Jan Marinissen (Philips Research Labs, The
  Netherlands)
• 26 Institutions representing 100 researchers
  (most of our industrial colleagues not yet
  included, 60 and 200 in QUEST EoI)

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Possible program of activities

• Integrating activities
• Not yet formally defined between partners but
  almost all participants have offered such
  activities
• Activities designed to spread excellence
• Satellite-based E-learning on SOC Test and
  Dependability (Torino, INESC, LIRMM, Stuttgart,
  UPC)
• Digital, Mixed-Signal and Memory Test Engineering
  Education (LIRMM, Agilent, Ljubljana, Stuttgart,
  Torino, UPC)
• Jointly executed researches
• Defect Based Test methods for nanometer ICs
  (Balearic Islands, Bologna, Freiburg, INESC,
  LIRMM, UPC) (Warsaw, Bratislava, Tallinn)
• Processor-based SoC Test and Debug (Torino,
  Athens, INESC, LIRMM, Piraeus) LIP6

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Possible program of activities

• Jointly executed researches (cnt'd)
• Low Power Testing (LIRMM, INESC, Stuttgart, UPC)
• BIST of sequential circuits (Tallinn,
  Lingköping, Stuttgart)
• Testing Techniques for Reconfigurable
  System-On-Chip (LIRMM, INESC, Innsbruck,
  Stuttgart, Torino, Twente, UPC)
• Flexible Infrastructures for Testing
  Systems-on-a-Chip (Southampton, ARM Ltd,
  Innsbruck, Stuttgart)
• Fault Tolerant SOCs (Bologna, Athens, LIRMM,
  Piraeus, Postdam, Torino, UPC)
• Testable Design Test of Embedded Analogue Cores
  in SoC (Twente, INESC, LIRMM, Sevilla, TIMA)
  (Cantabria)

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Possible program of activities

• some orphans
• Hierarchical Test (Tallin)
• SOC testing of digital parts based e.g. on IEEE
  P1500 standard (Bratislava)
• Design of effective built-in self-test structures
  for VLSI circuits (Gliwice)
• Convergence of verification and testing (Verona)

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List of top level researchers in this field

• The European Test community is quite well
  organized
• European Group of the IEEE TTTC (Chair J.
  Figueras, Vice-Chair Z. Peng)
• All top level European academic researchers
  included in the Eurosoc proposal
• Still to work on the industrial participation

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Academic participation

• Athens (A. Paschalis)
• Balearic Islands (J. Segura)
• Bologna (C. Metra)
• Freiburg (B. Becker)
• INESC (J.P. Teixeira)
• Innsbruck (S. Hellebrand)
• LIRMM (M. Renovell)
• Piraeus (D. Gizopoulos)
• Postdam (M. Goessel)
• Sevilla (J.L. Huertas)

• Southampton (B. Al-Hashimi)
• Stuttgart (H.J. Wunderlich)
• TIMA (S. Mir)
• Politecnico di Torino (P. Prinetto, M. Sonza
  Reorda)
• Twente (H. Kerkhoff)
• UPC (J. Figueras)