FinFET SRAM Design - PowerPoint PPT Presentation

1 / 12
About This Presentation
Title:

FinFET SRAM Design

Description:

Body/Halo Doping. TSi. Gate. Source. Drain. Gate. Thin-body double ... Fin Height HFIN = W/2. Gate length = Lg. Fin Width = TSi. Drain. Gate1. Source. Switching ... – PowerPoint PPT presentation

Number of Views:1229
Avg rating:3.0/5.0
Slides: 13
Provided by: zhen5
Category:
Tags: finfet | sram | design | halo

less

Transcript and Presenter's Notes

Title: FinFET SRAM Design


1
FinFET SRAM Design
  • Zheng Guo
  • 11/09/2004

2
Increase SRAM Stability
  • Need to broaden operating margin or suppress
    variations.
  • Cut/boost node voltages
  • Difficult to apply and lower performance.
  • Increase ß-ratio
  • Difficult to only forward bias NMOS.
  • New devices?

Yamaoka, Hitachi, 2004
3
Double-gate MOSFET
  • Two gates achieve greater channel control.
  • Improved drive current from higher mobility and
    steeper sub-threshold swing.
  • More Scalable than a single gate Ultra-thin body
    (UTB) SOI device.

4
Thin-body double gate MOSFETs
Gate length Lg
Gate
Source
Fin Width TSi
Drain
Fin Height HFIN W/2
  • Back-gated (BG) MOSFET
  • Independent front and back gates
  • One switching gate and Vth control gate

Double-gated (DG) MOSFET
5
Compact Device Model
  • Semi-empirical device model based on a subset of
    BSIM3
  • Captures the effect of supply change, threshold
    shift, mobility enhancement
  • Parameters can be used to create Spectre AHDL
    models for DC simulation

6
6T SRAM Cell
  • All FETs double-gated.
  • Access NFETs back-gated w/ feedback to
    dynamically increase ß-ratio by weakening access
    NFETs.
  • All other FETs double-gated.

7
4T SRAM Cell
  • Data retention leakage current usually need to be
    at least 1000xIleakage to compensate for the
    widely fluctuating leakage current.
  • Data retention leakage current flows on both
    sides but only needs to flow in one side for
    dataretention.

Yamaoka, Hitachi, 2004
8
4T SRAM Cell
  • All FETs double-gated.
  • Access PFETs back-gated w/ feedback to
    selectively increase compensation current and to
    dynamically increase ß-ratio.
  • All other FETs double-gated.

9
4T Write Issue
  • When writing to a neighboring cell (sharing
    common bit-lines), ICOMP is reversed and will
    discharge the 1 storage node!
  • Level of discharge depends on VT of the access
    PMOS transistors.
  • Use high VT devices.

10
4T Write Issue
  • Moderate VT access devices
  • 110 surface conduction

11
4T Write Issue
  • High VT access devices
  • 110 surface conduction
  • WL-0.2V on Read/Write.

12
Layouts
6T Cell
4T Cell
6.6um X 8um
5um X 8um
Write a Comment
User Comments (0)
About PowerShow.com