Development of Bondgraph Models for Power Electronic Systems

1
A Reduced Switch Count 5-Level Inverter With
Common-Mode Voltage Elimination and capacitor
voltage balancing For an Open-End Winding IM
Drive
Gopal Mondal Centre for Electronics Design and
Technology Indian Institute of Science,
Bangalore INDIA 560012
2
Flow of presentation

• Multi-level inverters
• Previous work
• Motivation
• Proposed Scheme
• Implementation of the proposed Scheme
• Experimental Results
• DC-link capacitor voltage balancing an open loop
  control scheme
• Implementation of the Closed loop capacitor
  voltage balancing
• Experimental Results
• Speed Reversal

3
Multi-level inverters
4
Multi-level inverters

• Multi-level inverters are the preferred choice
  in industry for the application in High voltage
  and High power application
• Advantages of Multi-level inverters
• Higher voltage can be generated using the devices
  of lower rating.
• Increased number of voltage levels produce better
  voltage waveforms and reduced THD.
• Switching frequency can be reduced for the PWM
  operation.

5
A five-level inverter for the open end winding IM
drive
Previous work
The 5-level inverters (Inverter-I and
Inverter-II) at both the end of the open end
winding induction motor are realised by cascading
two 2-level inverters and one 3-level (NPC)
inverter.
Fig.-1
6
space vector locations for inverter-I or
inverter-II
Previous work
For each inverters (inverter-I and inverter-II)
total 125 switching states available which are
distributed over the 61 voltage vector points
creating a 5-level voltage vector structure
Fig.-2
7
Combined voltage space vector structure of a dual
five-level inverter fed open-end winding
induction motor drive
Previous work
Combined voltage vectors of inverter-I and
inverter-II giving a 9-level voltage vector
structure. There are 15625 switching states
distributed over 217 voltage space vector point.
Fig.-3
8
Common mode voltage (CMV)
Previous work

• Because of the common DC- sources at both end of
  the inverters, there will be circulating current
  called the common mode current due to the common
  mode voltage.
• CMV for inverter-I is defined as
• VCMA (VAO VBO VCO) / 3.
  (1)
• CMV for inverter-II is defined as
• VCMA (VAO VBO VCO) / 3.
  (2)
• Equivalent common-mode voltage for the combined
  inverter system (CMV generated at the inverter
  phases) is
• VCM VCMA VCMA
• If the nine level voltage vector is generated
  without common mode voltage, there are 8 DC
  sources required instead of four.

9
Common mode voltages and its effects
Previous work

• PWM inverters generate high frequency, high
  amplitude common mode voltages, which induces
  shaft voltage on the rotor side
• When the induced shaft voltage exceeds the
  breakdown voltage of the lubricant in the
  bearings, result in large bearing currents
• This damages the bearings, leading to motor
  failures and also causes EMI
• PWM inverters which do not generate common mode
  voltage are suggested as a solution to the above
  problems

10
Voltage vectors with zero common mode voltage for
the inverter-I and Inverter-II
Previous work
To eliminate the common mode voltage only those
switching states has zero common mode voltage are
chosen for the PWM switching. 19 voltage vectors
with 19 switching states has zero common mode
voltage. Switching states with zero common mode
voltage Produce a 3-level voltage space vector
structure
Fig.-4
11
Combined voltage vector structure of inverter-I
and Inverter-II
Previous work

• Combination of the two three-level voltage space
  vector structure will give a five-level
  structure.
• There are 361 switching states distributed
  over 61 voltage vector points

Fig.-5
12
Previous work

• The power circuit uses total 48 switches.
• Redundant switching states are used for the
  common mode voltage elimination and closed loop
  DC-link capacitor voltage balancing.
• Number of voltage sources can be reduced and two
  voltage sources are enough with four DC-link
  capacitors to implement the five level voltage
  waveform.

13
Previous work
The reduced power circuit with less number of
voltage sources is-
14
Previous work
Fig.-6
15
Motivation

• There are 361 switching states available for 61
  voltage space vector locations for the five level
  inverter discussed. But only few are used for the
  common mode voltage elimination and DC-link
  capacitor voltage balancing.
• It implies that the number of redundant switching
  states can be reduced keeping the performance of
  the inverter same.
• It is observed that by reducing the power circuit
  structure it is possible to maintain the same
  performance of the inverter.

16
The propose power circuit of the five-level
inverter for open-end winding induction motor
drive
Proposed Scheme
Fig.-7
17
The propose power circuit of the 5-level inverter
Proposed Scheme

• The five-level inverters (Inverter system-A and
  Inverter system-A) are realised by cascading Two
  2-level and a three-level inverters.
• Two 2-level inverters are common to both the
  inverter system-A and Inverter system-A

Fig.-7b
18
The propose power circuit of the five-level
inverter for open-end winding induction motor
drive
Proposed Scheme
Complementary Switches for leg-A of inverter
system-A S11 and S14 S21 and S34 S31 and
S24 S41 and S44 Similar for the other phases
Fig.-7a
19
The propose power circuit of the 5-level inverter
Proposed Scheme

• Due to the power circuit structure some of the
  available redundant switching states are reduced,
  
• but the available switching states are sufficient
  for the common mode elimination and DC-link
  capacitor voltage balancing.

Fig.-7b
20
Proposed Scheme
Combined voltage space vector locations for
5-level inverter with zero common mode voltage
Fig.-7c
21
Proposed Scheme
Combined voltage space vector for 5-level
inverter with zero common mode voltage
Fig.-7c
22
Proposed Scheme
Combined voltage space vector for 5-level
inverter with zero common mode voltage
Switching states for the voltage vector A1
(-101,-202), (10-1,000), (000,-101),
(20-2,10-1), (01-1,-110), (02-2,-12-1), (0-11,-1
-12), (-12-1,-220), (11-2,01-1), (1-10,0-11),
(1-21,0-22), (2-1-1,1-10), (-110,-211),
(2-20,1-21)
Fig.-7c
23
Some of the switching states are impossible for
Fig-II
Proposed Scheme
Switching state(2-1-1,1-10) possible
Switching state (2-1-1,1-10) impossible
Fig.-II. Proposed power circuit
Fig.-I. Previous power circuit
Fig.-7d
24
Previous Scheme
Combined voltage space vector for 5-level
inverter with zero common mode voltage
Switching states for the voltage vector A1
(-101,-202), (10-1,000), (000,-101),
(20-2,10-1), (01-1,-110), (02-2,-12-1), (0-11,-1
-12), (-12-1,-220), (11-2,01-1), (1-10,0-11),
(1-21,0-22), (2-1-1,1-10), (-110,-211),
(2-20,1-21)
Fig.-7c
25
Proposed Scheme
Combined voltage space vector for 5-level
inverter with zero common mode voltage
Switching states for the voltage vector A1
(-101,-202), (10-1,000), (000,-101),
(20-2,10-1), (01-1,-110), (02-2,-12-1), (0-11,-1
-12), (-12-1,-220), (11-2,01-1), (1-10,0-11),
(1-21,0-22), (2-1-1,1-10), (-110,-211),
(2-20,1-21)
Fig.-7c
26
The propose power circuit of the 5-level inverter
Proposed Scheme

• Number of redundant switching states are less for
  this power circuit compared to the previous
  one(361).
• There are 241 switching states possible for The
  present scheme(61 voltage space vector locations)
• But the available switching states are sufficient
  for the common mode voltage elimination and
  DC-link capacitor voltage balancing

Fig.-7e
27
Selection of the Switching states for the
elimination of common mode voltage
Proposed Scheme

• Common mode voltage is eliminated by
  selecting the switching states which have zero
  common mode voltage.
• Switching states are selected in such a way, that
  the pole voltage have the half-wave symmetry and
  there is no even harmonics in both pole and phase
  voltages

Fig.-8
28
Proposed Scheme
Speed control scheme
A simple V/f control is used for the
implementation of the proposed five-level
inverter. The PWM strategy is automatically
calculating the switching time for the voltage
vectors and the switching states are selected
from the look up table in the FPGA.
29
Experimental Results

• (a) Simulation result
  (b) experimental result
• Fig.9(a),(b) top and bottom are Pole voltages
  VOA and VOA and the middle one is machine phase
  voltage VAA for switching the inner Sectors.
• Y-axis 1div50V, X-axis 1div0.02 sec

30
Experimental Results

• (a) Simulation result
  
  (b) experimental result
• Y-axis 1div50V,1div1A, X-axis 1div0.01
  sec Y-axis 1div50V, 1div5A, X-axis
  1div0.02 sec
• Fig.10(a),(b) Phase voltage and phase current
  for switching the inner Sectors.

31
Experimental Results

• (a)
  
  (b)
• Fig.11(a),(b) Y-axis
  normalized amplitude, X-axis order of
  harmonics

32
Experimental Results

• (a) Simulation result
  (b) experimental result
• Fig.12(a),(b) top and bottom are Pole voltages
  VOA and VOA and the middle one is machine phase
  voltage VAA for three-level of operation
• Y-axis 1div50V, X-axis 1div0.02 sec

33
Experimental Results

• (a) Simulation result
  
  (b) experimental result
• Y-axis 1div50V,1div1A, X-axis 1div0.01
  sec Y-axis 1div50V, 1div5A, X-axis
  1div0.02 sec
• Fig.13(a),(b) Phase voltage and phase current
  for three-level of operation.

34
Experimental Results

• (a)
  
  (b)
• Fig.14(a),(b) Y-axis normalized
  amplitude, X-axis order of harmonics

35
Experimental Results

• (a) Simulation result
  (b) experimental result
• Fig.12(a),(b) top and bottom are Pole voltages
  VOA and VOA and the middle one is machine phase
  voltage VAA for four-level of operation
• (a) Y-axis 1div50V, X-axis 1div0.02 sec
• (b) Y-axis 1div50V, X-axis 1div0.01 sec

36
Experimental Results

• (a) Simulation result
  
  (b) experimental result
• Y-axis 1div50V,1div1A, X-axis 1div0.02
  sec Y-axis 1div50V, 1div5A, X-axis
  1div0.01 sec
• Fig.13(a),(b) Phase voltage and phase current
  for four-level of operation.

37
Experimental Results

• (a)
  (b)
• Fig.14(a),(b) Y-axis normalized
  amplitude, X-axis order of harmonics

38
Experimental Results

• (a) Simulation result
  (b) experimental result
• Fig.12(a),(b) top and bottom are Pole voltages
  VOA and VOA and the middle one is machine phase
  voltage VAA for five-level of operation
• Y-axis 1div50V, X-axis 1div0.005 sec

39
Experimental Results

• (a) Simulation result
  
  (b) experimental result
• Y-axis 1div50V,1div1A, X-axis 1div0.01
  sec Y-axis 1div50V, 1div5A, X-axis
  1div0.01 sec
• Fig.13(a),(b) Phase voltage and phase current
  for five-level of operation.

40
Experimental Results

• (a)
  
  (b)
• Fig.14(a),(b) Y-axis normalized
  amplitude, X-axis order of harmonics

41
DC-link capacitor voltage balancing
42
DC-link capacitor voltage balancing

• With Proper DC link capacitor balancing the four
  DC-link voltage sources can be reduced to TWO

43
DC-link capacitor voltage balancing
Fig.16. Reduced power circuit with capacitor
voltage balancing
44
DC-link capacitor voltage balancing- an Open loop
control scheme

• Two switching states are selected at locations
  for DC link balancing along with common mode
  voltage elimination,
• The selected two switching states at a particular
  location has opposite effect on DC link capacitor
  balancing
• So in Two sampling periods the DC link capacitor
  charges balance can be achieved
• In locations where there is no effect on the
  DC-link capacitors, only one switching state is
  used for CME

45
DC-link capacitor voltage balancing- an Open loop
control scheme
Two switching states for the same voltage vector
Motor phase connections for different switching
states
Fig.-17
46
DC-link capacitor voltage balancing- an Open loop
control scheme
Current through C4iCiA C3iA C2iC C1iCiA
Two switching states for the same voltage vector
Current through C4iCiA C3iC C2iA C1iCiA
Fig.-17
47
DC-link capacitor voltage balancing- an Open loop
control scheme

• After two switching interval total current
  through
• C42(iCiA)
• C3 iCiA
• C2 iCiA
• C12(iCiA)
• gtVc4 Vc1 and Vc2 Vc3
• (000,-101) and (10-1,000) are complementary pairs

48
DC-link capacitor voltage balancing- an Open loop
control scheme
Switching state with no effect on DC-link
capacitor voltages

• Current through
• C4iCiA
• C30
• C20
• C1iCiA
• gtVc4 Vc1 and Vc2 Vc3

Fig.-18
49
DC-link capacitor voltage balancing- an Open loop
control scheme
Fig.-19. (a) Voltage and current waveform for the
operation of the motor From zero speed to the
5-level of operation
50
DC-link capacitor voltage balancing

• Open loop capacitor voltage balancing works well
  for the ideal conditions.
• For any abnormal conditions like
• Sudden short circuit,
• Asymmetry in PWM pulses,
• Unequal DC-link capacitors etc.
• Closed loop capacitor voltage balancing is
  required

51
DC-link capacitor voltage balancing
Closed loop capacitor voltage balancing with
capacitor voltage sensing
It is sufficient to maintain the equal voltage
between the capacitor pairs C4, C1 and C3, C2
There are three condition can happen in each
pair of capacitors- C4 gt C1 (controller
state)C1H C4 C1 C1N C4 lt C1 C1L C3 gt C2 C2H C3
C2 C2N C3 lt C2 C2L (H -gt High, N-gt Normal,
L-gt Low)
Fig.-20
52
DC-link capacitor voltage balancing
So the both pair of capacitors will generate
together nine controller states
C4 gt C1 (controller state)C1H C4 C1 C1N C4 lt C1
C1L C3 gt C2 C2H C3 C2 C2N C3 lt C2 C2L (H -gt
High, N-gt Normal, L-gt Low)
53
DC-link capacitor voltage balancing
The switching state (01-1, -110) can be used
as the corrective state for the controller state
C1NC2L and the switching state (1-10,0-11) can
be used as the corrective state for the
controller state C1NC2H
C1NC2H C1NC2L
Fig.-21
54
DC-link capacitor voltage balancing
Implementation of the Closed loop capacitor
voltage balancing
55
Experimental Results
Fig.-22
Variation of capacitor voltage during enabling
and disabling of the controller (Operation in
2-level)
Variation of capacitor voltage during enabling
and disabling of the controller (Operation in
3-level)
Fig.-23
56
Experimental Results
Variation of capacitor voltage during enabling
and disabling of the controller (Operation in
4-level)
Fig.-24
Variation of capacitor voltage during enabling
and disabling of the controller (Operation in
5-level)
Fig.-25
57
Experimental Results
Variation of capacitor voltage during enabling
and disabling of the controller (operation in
Over modulation region)
Fig.-26
Variation of capacitor voltage during enabling
and disabling of the controller (12-step of
Operation)
Fig.-27
58
Speed reversal
59
Speed reversal
Strategy of DC-link capacitor balancing during
speed reversal

• Two comparators are used for the capacitor
  balancing in speed reversal of the
  motor.
• First comparator will check the unbalance in the
  capacitor voltages. Second comparator will check
  whether the error is increasing or decreasing.
• Initially the controller will select the
  switching states for the motoring mode, but if
  the error is increasing it will select the
  switching states for the generating mode.

60
Speed reversal
Strategy of DC-link capacitor balancing during
speed reversal
Switching states for the controller states will
interchange
61
Speed reversal
(a)
(b)
Fig.-27.(a) Voltage and current waveform during
machine speed reversal. (b) Capacitor voltages
62
A Front end Switched Rectifier DC Source for
Neutral Point Balancing of A NPC Three-Level
Inverter for The Full Modulation Range
K.Sivakumar , Sukumar de, K.Gopakumar , Gopal
Mondal CEDT, Indian Institute of
Science,Bangalore-560012, INDIA and Keith
Corzine Dept.of EE,University of Missouri, Rolla,
USA

63
Contents

• Introduction
• Review of NPC three-level inverter
• Proposed circuit topology to reduce the DC-
  neutral point
• fluctuations
• Simulation results and discussion
• Experimental verification of the proposed
  topology
• Conclusion

64
Conventional three-level NPC inverter

• Capacitor balancing problems exists with a single
  DC Link
• Two separate DC link can solve the problem of
  neutral point fluctuations, but with increased
  cost and complexity.

65
Space-vector combinations of three level NPC
inverter
66
Switching state groups based on the DC capacitor
charging and discharging

• Group-A switching states will not create any
  voltage unbalance problems in capacitors
• Group-B and Group-C switching states will create
  voltage unbalance problems in capacitors, with a
  single DC Link

67
Proposed Switched Voltage Source Three level NPC
Inverter

• In the proposed topology only one active voltage
  source is used with a magnitude of Vdc/2
• The rated DC link voltage can be obtained by
  switching the voltage source (Vdc/2) between the
  top (C1) and bottom (C2) capacitors with a duty
  ratio of 0.5.
• The DC link switching is independent of the
  inverter switching control

68
Source capacitor C is parallel to the Capacitor
C1 when S1 is ON
69
Source capacitor C is parallel to the capacitor
C2 when S2 is ON
70
The DC Link Voltage Control
Top trace is output voltage of the diode bridge
rectifier and bottom trace is gating pulse of the
extra switch S1 X axis 2ms/div), fsw300Hz
Top trace is output voltage of the diode bridge
rectifier and bottom trace is gating pulse of the
extra switch S1 (Scale X axis 2ms/div).
For an n pulse rectifier fsw N ((n f1)/2)
Where fsw minimum Switching frequency of
extra switches f1 Supply frequency
N odd integer
71
Simulation and experimental Results

• The proposed topology is simulated with a 4kW
  three phase induction motor as load and
  experimentally verified on 1kW Induction motor.
• It is tested for entire range of speeds by using
  V/f control
• The inverter switching frequency is 1 kHz
• the extra switches which are used to get full DC
  link voltage are switched at constant frequency
  of 600Hz.
• The value of each capacitor is 1000µF.
• the gating signals are generated using TMS320 F
  2812 DSP and GAL22V10 platforms

72
Experimental Results for modulation index 0.4
Top trace is Pole voltage bottom trace is phase
current X-axis 10 ms/div Y-axis 50 V/div and
0.3A/div
Top three traces are Capacitor Voltages bottom
trace is Switched rectifier current to C1 X-
axis 2.5 ms/div, Y-axis 20V/div and 1A/div
73
Top trace is phase voltage, Second trace is
voltage across the switch S1, Third trace is
phase current Fourth trace is Switched rectifier
current to C1 X-axis 10 ms/div, Y-axis 50V/div
and 1A/div.
74
Two level inverter operation
Top trace is phase voltage (Van) Y-axis
50V/div, second trace is Pole voltage(Vao)
Y-axis 50V/div, third trace is line voltage
(Vab)Y-axis 100V/div Fourth trace is Phase
current Y-axis 1A/div and X-axis 10ms/div
75
Experimental Results for modulation index 0.8
Top trace - Pole Voltage second trace - Phase
current (Scale X-axis 5ms/div, Y-axis 50V/div
and 0.5A/div)
Top Trace voltage across the capacitor C,
Second trace - voltage across the Capacitor C1
Third trace - voltage across the capacitor C2
76
Experimental Results for modulation index 0.8
Top trace - Phase voltage Phase Voltage, Second
trace - Extra Switch voltage, Third trace -
Switch Current (Scale X-axis 5ms/div, Y-axis
50V/div and 2A/div)
77
Experimental Results for Over-modulation
Top trace is pole voltage bottom trace is phase
current X-axis 2.5 ms/div Y-axis 50 V/div and
1A/div.
Top three traces are capacitor voltages bottom
trace is switch (S1) current X- axis 10 ms/div,
Y-axis 20V/div and 1A/div.
78
Experimental Results for Over-modulation
Top trace is phase voltage, second trace is
voltage across the input switch, third trace is
phase current Fourth trace is Switch
current X-axis 5 ms/div, Y-axis 50V/div, 1A/div
(third trace) and 2A/div(fourth trace).
79
Transient performance of the proposed drive
topology.
Top trace is phase voltage bottom trace is phase
current during the acceleration from 20Hz to
40Hz X-axis 500ms/div, Y-axis 50V/div and
2A/div
80
Transient performance of the proposed drive
topology.
Top trace is pole voltage bottom trace is phase
current during the acceleration form 15Hz to
30Hz X-axis 500ms/div, Y-axis 50V/div and 2A/div
81
Transient performance of the proposed drive
topology.
Top trace is capacitor voltage Bottom trace is
phase current during the acceleration form 20Hz
to 40Hz X-axis 500ms/div, Y-axis 50V/div and
2A/div
82
CONCLUSION

• In the proposed topology the voltage fluctuations
  of the neutral point are considerably reduced by
  switching the voltage source between two
  capacitors at constant frequency independent of
  NPC inverter operation.
• The DC link Voltage required is half compared to
  the conventional three level NPC inverter. The
  rating of all the devices used in proposed
  topology is equal to the source voltage (i.e.
  Vdc/2).
• This configuration needs only one power supply
  compared to an H-bridge topology and cascading of
  two two-level inverters topology, which needs
  three isolated DC links and two isolated DC links
  respectively.

83
12-sided polygonal voltage space vector structure
for induction motor drive

• By
• Prof. K. Gopakumar
• CEDT, Indian Institute of Science, Bangalore

84
Flow of presentation

• Motivation for the present research.
• Some of the schemes to be presented
• Hybrid space vector PWM strategy in linear and
  over-modulation region involving hexagonal and
  12-sided polygonal space vector structure.
• Development of two concentric 12-sided polygons
  using conventional 3-level inverters with
  capacitor balancing.
• Further refinement of the above space vector
  structure into multiple 12-sided polygons with
  conventional 3-level inverters.
• Discussion on experimental verification of the
  above schemes
• Steady state operation.
• Transient results with motor accelerated upto
  rated speed with open-loop V/f control
• Harmonic performance of phase voltage and phase
  current under these conditions
• Conclusion

85
Current Technology- Multilevel inverters

• Multi level inverters are popular for high power
  drives because of low switching losses and low
  harmonic distortion in the output voltage.
• In conventional structure ,voltage vectors lie
  on the vertices of a hexagon. So in the extreme
  modulation range there is a possibility of
  producing (6n1) harmonics in the phase current
  waveform.
• With low switching frequency for high power
  drives, the (6n1) harmonics in the current
  waveform can produce torque pulsation in the
  drive . The problem is particularly severe in
  over-modulation region where the (6n1) harmonics
  constitute a major portion of the total current.
• In this respect polygonal voltage space vector
  structures with sides more than six, is very
  desirable for high power drives.

86
Proposed research schemes

• A 12-sided polygonal space vector structure for
  IM drive has already been proposed using
  conventional 2-level inverters. This has the
  advantage of eliminating all (6n1) harmonics in
  the phase current waveform throughout the
  modulating range. However, one drawback of the
  scheme is the high dv/dt stress on the devices,
  since each inverter switches between the vertex
  of the 12-sided polygon and the zero vector at
  the centre.
• In the proposed work, a multilevel inverter
  topology is described which produces a hexagonal
  space vector structure in lower-modulation region
  and a 12-sided polygonal space vector structure
  in the higher modulation region.
• In another scheme, a multilevel voltage space
  vector structure with vectors on the 12-sided
  polygon is generated by feeding an open-end
  winding IM drive by two three level inverters.
• In a third scheme, a high resolution PWM
  technique is proposed involving multiple 12-sided
  polygonal space vector structure, that can
  generate highly sinusoidal voltages at a reduced
  switching frequency.

87
A Hybrid Space Vector PWM involving Hexagonal and
12-sided polygonal voltage space vector structures
88
Topology of a multilevel inverter for generation
of 12-sided polygonal voltage space vector

• Consists of three cascaded 2-level inverters.
• The switch status for different levels of pole
  voltage are shown below. These are defined with
  respect to the lower rail of the dc bus.

C
D
A
Switch status for different levels of pole voltage
B
O
Pole voltage of overall inverter-vAO Pole voltage
of INV3- vBO Pole voltage of INV2-vAB Pole
voltage of INV1-vCD
89
Transformer connection for generation of 12-sided
polygonal voltage space vector

• Asymmetrical DC-links are easily realized by a
  combination of star-delta transformers, since
  0.634kVdcv3 x 0.366kVdc.

90
Voltage space vector structure of the proposed
scheme
End of linear modulation

• Consists of four concentric hexagonal structures
  with different radii (0.366kVdc, 0.634kVdc, 1kVdc
  and 1.366kVdc)
• Operates in the inner hexagons at lower voltage
  to retain the advantages of multilevel inverter
  like low switching frequency.
• At higher voltage, the outermost hexagon and the
  12-sided polygonal space vector structure is used
  resulting in highly suppressed 5th and 7th order
  harmonics.
• The leads to 12-step operation at rated voltage
  operation, leading to the complete elimination of
  6n1 harmonics. (nodd) from the phase voltage.

OE 1.225kVdc
91
Some additional points on generation of space
vectors

• The modulation index (m), is defined as the ratio
  of the length of the reference vector to the
  length of the radius of the 12-sided polygon
  which extends upto 0.965 in linear modulation
  range and is equal to 1 at 12-step operation.
• The total dc link voltage for the inverter is
  1.366kVdc and the radius of the 12-sided polygon
  is 1.225kVdc. If the radius of the 12-sided
  polygonal space vector structure is equal to the
  radius of a conventional hexagonal space vector
  structure, then the value of k is taken as
  1/1.2250.816.
• For k 0.816, the maximum phase voltage
  available in linear modulation is 0.637Vdc and
  equal to 0.658Vdc in 12-step mode of operation.
• For comparison purpose, if the maximum
  fundamental voltage available in 6-step mode and
  12-step mode are made equal to 0.637Vdc, then k
  is to be chosen as 0.789.
• For k 0.789, in 12-sided polygonal structure,
  the maximum phase voltage available in linear
  modulation is 0.615Vdc and equal to 0.637Vdc in
  12-step mode of operation. There is an increase
  in linear modulation range.

92
Modulating waveform

• The modulating waveform for phase-A for 35Hz
  operation (linear modulation range) is shown.
• The modulating waveform is synchronized with the
  start of the sector (sampling interval is always
  a multiple of twelve).
• Because of asymmetric voltage levels, three
  asymmetric synchronized triangles are used their
  amplitudes are in the ratio 0.3660.6340.366.

93
Switching sequence analysis

• Three pole voltages are shown for a 60 degree
  interval at 35Hz operation.
• In A phase the voltage level fluctuate between
  levels 3 and 2 , and in C phase the
  voltage level fluctuates between levels 1 and
  0 .
• The sequence in which the switches are operated
  are as follows (200), (210), (211), (311),
  (321), (311), (211), (210), (211), (311), (321),
  (211), (221), (321), (221), (210), (220), (221),
  (321), (331), (221), (220),
  where the numbers in brackets indicate the level
  of voltage.
• This sequence corresponds to 2 samples per
  sector.

94
Experimental Setup

• A digital signal processor (DSP), TMS320LF2812 is
  used for experimental verification.
• For different levels of output in the pole
  voltage, three carriers are required. However, it
  is difficult to synthesize three carrier waves in
  the DSP, as such only one carrier is used and the
  modulating wave is appropriately scaled and level
  shifted.
• A 3.7kW induction motor was fed by the proposed
  inverter operating under open loop constant V/f
  control at no load. The motor was made to run
  under no load in order to show the effect of
  changing PWM patterns of the generated voltage on
  the motor current, particularly during transient
  conditions.
• In order to keep the overall switching frequency
  within 1 KHz, number of samples is decided as
  follow
• Upto 20 Hz operation 4 samples per sector.
• 20 Hz-40 Hz 2 samples per sector.
• Beyond 40 Hz 1 sample per sector-extending up to
  final 12-step mode.
• Individual inverters are switched less than half
  of the total cycle.

95
Experimental results-Operation at 10 Hz
Normalized harmonic spectrum of
Phase current
Phase voltage
Phase voltage
Phase current
Phase voltage and current waveforms

• Switching happens within the innermost hexagon
  space vector locations.
• As seen from the pole voltage waveforms, only the
  lower inverter is switched while the other two
  inverters are off, hence the switching loss is
  low.
• Four samples are taken in each sector, so INV3
  switching frequency is (12x4X10480Hz). The first
  carrier band harmonics also reside around 48
  times fundamental.

Space Vector
Overall inverter
INV3
Inverter Topology
INV2
INV1
Pole voltage waveforms
96
Experimental results-Operation at 30 Hz
Normalized harmonic spectrum of
Phase current
Phase voltage
Phase voltage
Phase current

• The space vector locations that are switched lie
  on the boundaries of the second and third hexagon
  from the center.
• Number of samples are reduced from four to two,
  thus switching frequency is (fs12X2x30720Hz).
• INV3 and INV1 are switched about 1/3rd of the
  total cycle, while INV2 is switched about 20 of
  the cycle.

Phase voltage and current waveforms
Overall inverter
Space Vector
INV2
INV2 switches
INV3
INV1
Pole voltage waveforms
Inverter Topology
97
Operation at 47 Hz ( end of linear modulation
range)
Normalized harmonic spectrum of
Phase current
Phase voltage
Phase voltage
Phase current
Phase voltage and current waveforms
Overall inverter

• One sample is taken at the start of a sector, so
  switching frequency is only around (12X47564Hz).
• The space vector locations that are switched lie
  between the outer hexagon and the 12-sided
  polygon.

INV2
INV3
INV1
Space Vector
Pole voltage waveforms
98
Operation at 50 Hz ( 12-step operation)
Normalized harmonic spectrum of
Phase current
Phase voltage
Phase voltage
Phase current
Phase voltage and current waveforms

• Complete elimination of 6n1 harmonics (nodd)
  from the phase voltage.
• One sample is taken at the start of a sector
  (fs12X1x50600Hz).
• Each inverter is switched only once in a cycle.

Overall inverter
INV2
INV3
INV1
Pole voltage waveforms
Inverter Topology
99
Input current at 50 Hz ( 12-step operation)
Phase voltage
Phase current
Input phase voltage
Input line current

• The input current to the inverter is not peaky in
  nature, because of the presence of the star-delta
  transformers.

100
Motor acceleration with open loop V/f Control
Phase voltage
Phase current
Transition of motor phase voltage and current
from 24 samples to 12 samples per cycle at 40Hz
Transition of motor phase voltage and current
from outermost hexagon to 12-step operation.

• Because of the suppression of the 5th and 7th
  order harmonics, the motor current changes
  smoothly during the transition when the number of
  samples per sector is reduced from two to one at
  40Hz operation.
• As the speed of the motor is further increased,
  the inverter switching states pass through the
  inner hexagons and ultimately the phase voltage
  becomes a 12-step waveform.
• Under all operating conditions, the carrier is
  synchronized with the start of the sector.

101
Total Harmonic Distortion upto 100th harmonic
Harmonic performance of phase voltage and
current 10Hz 30 Hz 48.25 Hz 50Hz Voltage
THD 57.59 27.51 14.67 17.54 Voltage
WTHD 0.81 0.7 0.97 1.04 Current
THD 12.31 10.59 15.6 19.54 Current WTHD
0.28 0.45 1.2 1.5

• It is seen that voltage WTHD is quite low for all
  the operating conditions, as such the torque
  pulsation and harmonic heating in the machine is
  minimized.

102
Comparison with conventional structures

• A simplified comparative study is made between
  the proposed topology and the existing multilevel
  inverter configurations viz. 3-level NPC and
  4-level NPC inverters used for induction motor
  drives.
• The conduction and switching losses incurred in
  the inverter, and motor phase voltage harmonic
  distortions are numerically calculated by
  computer simulation for comparison.
• A linear turn-on and turn-off switching profile
  is used for loss calculation. Losses incurred in
  snubber circuits, protection circuits, gate
  drives and due to leakage currents are neglected.
  
• A 2.3kV, 373kW induction motor is driven by a
  3-level NPC, 4-level NPC and the proposed
  inverter. The inverter drives the induction motor
  under full load condition at around 0.85 p.f.
  lagging. Numbers of samples in a cycle are taken
  as 24.

103
Loss comparison with conventional structures

104
Observations

• The phase voltage WTHD for the proposed inverter
  shows considerable improvement, particularly at
  higher modulation indices and the 12-step mode of
  operation, because of the suppression or
  elimination of the 6n1 (nodd) harmonics.
• Conduction losses are more dominant than
  switching losses for IGBT made inverters. As
  such, presence of the clamping diodes in NPC
  inverters increases the total losses of the
  inverter. The proposed inverter does not have any
  clamping diode and is devoid of any such losses.
  The switching losses also remain low for the
  proposed inverter.
• It is seen that the conduction losses in the
  proposed inverter are always less than the
  conventional inverters. This is because in the
  proposed inverter, for any level of pole
  voltage output, two current carrying switches
  remain in conduction. This is not always the case
  in NPC inverters e.g. for a four level inverter,
  at higher modulation indices, three switches per
  phase carry the phase load current when the total
  dc bus voltage is obtained at the pole.
  Conduction losses in the proposed inverter are
  further less in over-modulation region because of
  the fact that the r.m.s. current in the inverter
  is less compared to conventional NPC inverters,
  due to the suppression or elimination of the 6n1
  (nodd) harmonics.

105
Synopsis

• A multilevel inverter topology is described which
  produces a hexagonal space vector structure in
  lower-modulation region and a 12-sided polygonal
  space vector structure in the higher modulation
  region.
• In the extreme modulation range, voltage vectors
  at the vertices of the outer 12-sided polygon and
  the vertices from the outer most hexagonal
  structure is used for PWM control, resulting in
  highly suppressed 5th and 7th order harmonics
  thereby improving the harmonic profile of the
  motor current. This leads to the 12-step
  operation at 50Hz where all the 5th and 7th order
  harmonics are completely eliminated.
• At the same time, the linear range of modulation
  extends upto 96.6 of base speed. Because of
  this, and the high degree of suppression of lower
  order harmonics, smooth acceleration of the motor
  upto rated speed is possible.
• Apart from this, the switching frequency of the
  multilevel inverter output is always limited
  within 1 kHz. The middle inverter ( high voltage
  inverter) devices are switched less than 25 of
  the output fundamental switching period.

106
Multilevel 12-sided polygonal voltage space
vector structures
107
Evolution of space vector structures (Hexagonal
and 12-sided)
Hexagonal space vectors.
12-sided polygonal space vectors.
E
S
R
F
4
3
5
6
2
G
Q
1
7
12
O
P
8
H
9
11
10
L
I
K
J
108
Multilevel 12-sided polygonal space vector
structure

• This is an extension of the single 12-sided
  polygonal space vector structure into a
  multilevel 12-sided structure.
• Compared to conventional 12-sided space vector
  structure, the device ratings and dv/dt stress on
  them are reduced to half.
• The switching frequency is also reduced to
  maintain the same output voltage quality.
• Here the added advantage is the complete
  elimination of 6n1 harmonics, nodd, from the
  phase voltage throughout the modulation index.
• The linear modulation range is also extended
  compared to the hexagonal structure.

109
Multilevel 12-sided polygonal space vector
structure

• Consists of two concentric 12-sided polygonal
  space vector structure.
• Unlike conventional hexagonal multilevel
  structure, here the sub-sectors are isosceles
  triangles rather than equilateral triangles.
• Each sector is thus divided into four sub-sectors
  as shown.

110
Inverter Structure

• In order to realize the proposed space vector
  structure, two conventional three level NPC
  inverters are used to feed an open ended
  induction motor.
• The two inverters are fed from asymmetrical dc
  voltage sources which can be obtained from the
  mains with the help of star-delta transformers
  and uncontrolled rectifiers.
• Because of capacitor voltage balancing of the
  NPC inverters, only two dc sources are used.

111
Algorithm for calculating switching times for
multilevel 12-sided polygonal space vector
structure

• Here, the timings for which adjacent vectors are
  switched are obtained as,
• This requires calculation of sine values through
  a look-up table, which takes unnecessary memory
  and time in a DSP.
• A better algorithm is proposed here which can
  calculate the timings by sampling the reference
  rotating phasor.

112
Algorithm for calculating switching times for
multilevel 12-sided polygonal space vector
structure

• 1. Any rotating phasor can be expressed as,

2. Transform (a,ß) into (a,b,c) and (a,b,c)
coordinates as
3. Multiply va, vb, vc etc. with the sampling
period Ts. Thus,
4. Calculate the following
113
Algorithm for calculating switching times for
multilevel 12-sided polygonal space vector
structure
5. Calculate the following
6. Since the timings change for each alternate
sector, an additional step is needed for
interchanging T1_12s and T2_12s.
OR
OR
OR
Then interchange the values of T1_12s and T2_12s.
114
Algorithm for calculating switching times for
multilevel 12-sided polygonal space vector
structure

• 7. For determining the sub-sectors following
  comparison is made,

If T1_12s lt 0.5Ts If T2_12s lt 0.5Ts
If (T1_12s T2_12s ) lt 0.5Ts then
Subsector-1. else Subsector-2.
else Subsector-3. else Subsector-4.
8. In sub-sector 1, T1 T1_12s, T2 T2_12s,
T0Ts-T1-T2. In sub-sector 2, T1 0.5Ts
T1_12s, T2 0.5Ts T2_12s, T0Ts-T1-T2.
In sub-sector 3, T1 T1_12s, T2 0.5Ts T2_12s,
T0Ts-T1-T2. In sub-sector 4, T1 0.5Ts
T1_12s, T2 T2_12s, T0Ts-T1-T2.
115
Experimental results-15 Hz operation
Normalized harmonic spectrum of
Phase voltage
Phase voltage
Pole voltage- high voltage inverter
Phase current
Pole voltage-low voltage inverter
Phase current

• Four samples are taken in each sector and
  switching takes place entirely in the inner
  12-sided polygon.
• The phase voltage harmonics reside at 15x12x4720
  Hz, which is 48 times the fundamental. However,
  the switching frequency of the pole voltage of
  INV1 is (24x15) 360Hz, while that of INV2 is
  (32x15) 480Hz.
• The higher voltage inverter switches about 50 of
  the cycle.

116
Experimental results-23 Hz operation
Normalized harmonic spectrum of
Phase voltage
Phase voltage
Pole voltage- high voltage inverter
Phase current
Pole voltage-low voltage inverter
Phase current

• Three samples are taken in each sector and
  switching takes place at the boundary the inner
  12-sided polygon. All the 6n1 harmonics, nodd,
  are absent from the phase voltage, while the rest
  are highly suppressed.
• The switching frequencies of the pole voltage of
  INV1 and INV2 are respectively (18x23) 414Hz and
  (24x23) 552Hz, with output phase voltage
  switching frequency at 828Hz (23x12x3).

117
Experimental results-40 Hz operation
Normalized harmonic spectrum of
Phase voltage
Phase voltage
Pole voltage- high voltage inverter
Phase current
Pole voltage-low voltage inverter
Phase current

• Two samples are taken in each sector and
  switching takes place between the inner and outer
  dodecagons.
• This is also seen in the phase voltage waveform,
  since the outer envelope of the waveform at lower
  frequency becomes the inner envelope at higher
  frequency.
• The harmonic spectrum of the phase voltage and
  current shows the absence of peaky harmonics
  throughout the range.

118
Experimental results-48 Hz operation
Normalized harmonic spectrum of
Phase voltage
Phase voltage
Pole voltage- high voltage inverter
Phase current
Pole voltage-low voltage inverter
Phase current

• This is the end of the linear modulation of
  operation.
• Here the number of samples per sector is two, as
  such the switching frequency sidebands reside
  around 24 times the fundamental. The switching
  frequency of the pole voltages of INV1 and INV2
  is respectively (48x12) 576Hz and (48x16)
  768Hz, with an output phase voltage switching
  frequency of 1152Hz (48x12x2).

119
Experimental results-49.9 Hz operation
Normalized harmonic spectrum of
Phase voltage
Phase voltage
Pole voltage- high voltage inverter
Phase current
Pole voltage-low voltage inverter
Phase current

• At the end of end over-modulation region, 24
  samples are taken in a sector, corresponding to
  the vertices of the polygon. The figure shows 24
  steps in the phase voltage.

120
Experimental results-50 Hz operation
Normalized harmonic spectrum of
Phase voltage
Phase voltage
Pole voltage- high voltage inverter
Phase current
Pole voltage-low voltage inverter
Phase current

• This is the 12-step operation, where one sample
  is taken at the start of a sector. The phase
  voltage and current is completely devoid of any
  5th and 7th order harmonics.

121
Total Harmonic Distortion upto 100th harmonic
Harmonic performance of phase voltage and current

• It is seen that voltage WTHD is quite low for all
  the operating conditions, as such the torque
  pulsation and harmonic heating in the machine is
  minimized.

122
Acceleration of the motor
Phase voltage
Phase current
Transition of motor phase voltage and current
from over-modulation to 12-step operation.
Transition of motor phase voltage and current
from inner to outer 12-sided polygon

• In both the cases, the motor current changes
  smoothly as the motor accelerates. This happens
  because of the use synchronized PWM and total
  elimination of 6n1 harmonics, nodd, from the
  phase voltage throughout the modulation index.

123
Capacitor balancing scheme

• The inner 12-sided polygonal space vector
  locations ( points 1-12) have four multiplicities
  which are complementary in nature in terms of
  capacitor balancing.
• The outer 12-sided polygonal space vector
  locations ( points 13-36) either do not cause any
  capacitor unbalancing, or have complementary
  states to maintain capacitor balancing.

124
Inner 12-sided polygon-switching multiplicities
for point-1
C2 is discharged, C4 is charged.
C1 is discharged, C4 is charged.
C1 is discharged, C3 is charged.
C2 is discharged, C3 is charged.
The four switching multiplicities are
complementary in nature in terms of capacitor
balancing.
125
Outer 12-sided polygon-switching multiplicities
Point-13, two multiplicities
C3 is discharged, C1 C2 are undisturbed.
C4 is discharged, C1 C2 are undisturbed.
Point-14 no multiplicity, no capacitor
disturbance
Point-36 no multiplicity, no capacitor
disturbance
126
Experimental Results-capacitor unbalancing at 20
Hz

• Capacitor unbalance is done at steady state with
  the motor running at 20 Hz speed.
• Both side capacitors are deliberately unbalanced
  and after some time controller action is taken.

Vc1, Vc2 Vc3, Vc4
Deliberate unbalancing
Controller action taken
C1,C2 higher voltage side capacitors C3,C4
lower voltage side capacitors
127
Experimental Results-capacitor unbalancing at 40Hz

• Both the sides are made unbalanced at the same
  time and are seen to come back to the balanced
  state.
• Compared to the 20 Hz case, it requires more time
  to restore voltage balance, since the number of
  multiplicities in the outer polygon is less.

Vc1, Vc2 Vc3, Vc4
Controller action taken
Deliberate unbalancing
C1,C2 higher voltage side capacitors C3,C4
lower voltage side capacitors
128
capacitor balancing during acceleration
INV1 Pole voltage
vC1, vC2
vC1-vC2
INV2 Pole voltage
vC3, vC4
Phase current
Capacitor voltages

• Capacitor voltages, pole voltages and phase
  currents during acceleration, showing the
  capacitor voltages are balanced throughout the
  operation.

129
Publication

• Anandarup Das, K. Sivakumar, Gopal Mondal, K
  Gopakumar, A Multilevel Inverter with Hexagonal
  and 12-sided Polygonal Space Vector Structure for
  Induction Motor Drive , published in IECON 2008,
  Nov 2008, pp 1077-1082.
• Anandarup Das, K. Sivakumar, Rijil Ramchand,
  Chintan Patel and K. Gopakumar, Multilevel
  Dodecagonal Space Vector Generation for Open-end
  Winding Induction Motor Drive Using Conventional
  Three Level Inverters , accepted for publication
  in EPE 2009.
• Anandarup Das, K. Sivakumar, Rijil Ramchand,
  Chintan Patel and K. Gopakumar, A Combination of
  Hexagonal and 12-sided Polygonal Voltage Space
  Vector PWM control for IM Drives Using Cascaded
  Two Level Inverters, to be published in May 2009
  issue of IEEE Transaction on Industrial
  Electronics.
• Anandarup Das, K. Sivakumar, Rijil Ramchand,
  Chintan Patel and K. Gopakumar, A Pulse Width
  Modulated Control of Induction Motor Drive Using
  Multilevel 12-sided Polygonal Voltage Space
  Vectors, accepted for publication in IEEE
  Transaction on Industrial Electronics.

130
Multiple 12-sided polygons

• With the same power circuit as above, it is
  possible to have multiple 12-sided polygonal
  space vector structure.
• Consists of six concentric 12-sided polygonal
  space vector structure.
• Very low voltage THD can be achieved using low
  switching frequency.
• Suitable for high power drives.

131
Conclusion

• A multilevel inverter topology is described which
  produces a hexagonal space vector structure in
  lower-modulation region and a 12-sided polygonal
  space vector structure in the over-modulation
  region. This leads to the complete elimination of
  6n1 harmonics (nodd) from the phase voltage at
  higher modulation index.
• A multilevel 12-sided polygonal space vector
  structure is proposed that does not have 6n1
  harmonics (nodd) throughout the modulation
  index. Capacitor balancing scheme is also
  proposed for the above scheme.
• These schemes result in improved voltage THD in
  the motor phase voltage and lower switching
  frequency operation which are very much desirable
  in high power drives.

132
A Hysteresis PWM Controller with Constant
Switching Frequency for Two-level VSI fed Drives
with Operation Extending to the Six-Step Mode

• Prof. K. Gopakumar
• CEDT, Indian Institute of Science
• Bangalore, INDIA

133
ORGANIZATION

• Introduction
• Current Error Space Phasor in VC SVPWM
• Parabolic Boundary for Current Error Space Phasor
• Vector Change Detection in Proposed Controller
• Sector Change Detection in Proposed Controller
• Simulation Results Experimental Results
• Conclusion

134
Introduction

• PWM Voltage Source Inverter (VSI)
• Voltage controlled PWM VSI
• Current controlled PWM VSI
• Current Controlled PWM VSI
• Advantages
• Simple, so can be implemented easily
• Excellent dynamic response
• Disadvantages
• Large current ripple in steady-state
• Generation of sub harmonic component in the
  current
• Variation in switching frequency

135
Introduction

• Current Controlled PWM VSI
• Can be classified into two
• Hysteresis Current Controller based VSI
• Ramp Comparison Controller based VSI
• Predictive Current Controller based VSI
• Other controllers
• On-off controller
• Neural network controller
• Fuzzy logic controller

136
Introduction

• Hysteresis Current Controller based VSI
• Fixed Tolerance band Hysteresis Current
  Controller based VSI
• Variable Tolerance band Hysteresis Current
  Controller based VSI

137
Introduction

• Fixed Tolerance band Hysteresis Current
  Controller based VSI
• Eliminates first two disadvantages of the
  conventional CC PWM VSI
• Its drawback is the variation of switching
  frequency in a fundamental cycle and with
  variation in the motor speed.
• Increased switching losses in the inverter
• Non-optimum current ripple
• Excess harmonic content in the load current
  causing overheating of the machine

138
Introduction

• Variable Tolerance band Hysteresis Current
  Controller based VSI

• Uses variable hysteresis band to keep the
  switching frequency constant.
• Examples are
• Adaptive hysteresis band
• Sinusoidal hysteresis band
• Disadvantages
• Complex to implement
• Stability problems
• Limitations in transient performance

139
Proposed Variable Band Hysteresis Current
Controller based VSI

• Continuously varying Parabolic Boundary for
  Current Error Space Phasor
• A new sector selection logic eliminating the two
  outer parabolas used in earlier work is proposed
  in the present work.
• This method uses the change in direction of the
  current error during sector change along any one
  of the orthogonal axes.

140
Current Error Space Phasor in VC SVPWM

• Power schematic of a three-phase (b)
  Voltage space phasor
• structure two-level VSI fed IM drive
  of the two-level VSI

141
Current Error Space Phasor in VC SVPWM
Basic switching vectors and Sectors

• 6 active vectors (V1,V2, V3, V4, V5, V6)

• Axes of a hexagonal
• DC link voltage is supplied to the load
• Each sector (1 to 6) 60 degrees

• 2 zero vectors (V0, V7)

• At origin
• No voltage is supplied to the load

Basic switching vectors and sectors.
142
Current Error Space Phasor in VC SVPWM

143
Current Error Space Phasor in VC SVPWM
Integrating both the sides

144
Current Error Space Phasor in VC SVPWM


145
Current Error Space Phasor in VC SVPWM

• at start of the Sector-1
• (? varies from 0? to 7? approximately)

(b) at middle of the Sector-1 (? varies from 27?
to 33? approximately),
Movement of current error space phasor (on ?-?
plane) in a few sampling intervals of VC-SVPWM
based two-level VSI fed IM drive when the
reference voltage space phasor
(c) at end of the Sector-1 (? varies from 54? to
60? approximately)
146
Current Error Space Phasor in VC SVPWM
Approximate theoretical boundary of current error
space phasor for VC-SVPWM based two-level VSI fed
IM drive for position of reference voltage space
phasor in Sector-1 for different operating
speeds (a) 10Hz operation, (b) 20 Hz operation,
(c) 30 Hz operation, and (d) 40 Hz operation

147
Parabolic Boundary for Current Error Space Phasor

• Four unique Parabolas acts as boundary for
  current error in sector-I.
• This parabolic boundary varies with the
  frequency.
• These parabolas are characterised by the
  equations
• For other sectors the boundary defined by these
  parabolas will remain the same, but their
  orientation will change.(i.e., the X axis and Y
  axis will change)

148
Vector Change Detection in Proposed Controller

• The amplitude of ?i is monitored along A, B, C,
  jA, jB and jC axes for vector selection
• The X axis and Y axis for parabolas for different
  sectors are shown in table given below

149
Vector Change Detection in Proposed Controller
VECTOR SELECTION FOR SECTOR- I (BASED ON INNER
PARABOLIC BANDS) FOR FORWARD DIRECTION OF
ROTATION OF MACHINE
150
Sector Change Detection in Proposed Controller
Simulation Results showing the variation of
current error along jA axis during sector change
for constant frequency VC SVPWM based two level
inverter (sector-3 to sector-4 change)
Current error during sector-1 to sector-2 change
151
Sector Change Detection in Proposed Controller

• The property of the current error space phasor
  that it will change its direction along one of
  the orthogonal axes jA, jB or jC during a sector
  change is utilized.

152
Sector Change Detection in Proposed Controller
Proposed sector change detection logic for
forward rotation of machine
( means continue with the same sector)
153
Block diagram of the experimental setup
154
Simulation Results
10Hz operation for VC-SVPWM
155
Simulation Results Experimental Results
Simulation Experimental results at 10Hz
operation for Proposed Hysteresis Controller
156
Simulation Results
10Hz operation for VC-SVPWM
157
Simulation Results
Simulation results at 10Hz operation for Proposed
Hysteresis Controller
158
Simulation Results
30Hz operation for VC-SVPWM
159
Simulation Results Experimental Results
Simulation Experimental results at 30Hz
operation for Proposed Hysteresis Controller
S