Development of Bondgraph Models for Power Electronic Systems

1
Power Converters and Drives Lab -a Research
Overview
Prof. K. Gopakumar Centre for Electronics Design
and Technology Indian Institute of Science,
Bangalore INDIA 560012
2
Conventional two-level inverter structure
S1
S5
S3
A1
B1
C1
Vdc
S4
S2
S6
Induction motor
3
SVPWM for conventional two-level inverter
V
cs
as
V
/2
dc
C1
0
-V
/2
dc
wt
4
Pole voltage waveforms in conventional two-level
inverter
5
Phase voltage waveforms in conventional two-level
inverter
Phase voltage
Phase current
6
Presentation outline

• Multilevel inverters
• Topologies
• Inverter topologies cascading two level inverters
• Inverter topologies with open-end IM drive
• Inverter topologies with asymmetric DC link
  voltages
• Multilevel inverter topologies for common mode
  voltage elimination
• Two-level inverter scheme with common mode
  voltage elimination
• Higher level of multilevel inverter scheme
• DC-link capacitor voltage balancing winding
  induction motor drive
• Three-level structure with single power supply
• PWM signal generation for multilevel inverter
• A Space Phasor Based Self Adaptive Current
  Hysteresis Controller
• Multi-phase (six-phase) and multi motor drive
• Sensorless control scheme for IM drive
• 12-sided polygonal voltage space phasor
  generation.

7
Multilevel inverters
8
Advantages of multilevel inverters over the
two-level inverters

• Synthesis of higher voltage levels using power
  devices of lower
• voltage ratings
• Increased number of voltage levels which leads
  to better voltage
• waveforms and reduced Total Harmonic
  Distortion (THD) in voltage
• Reduced switching stresses on the devices

9
Neutral clamped inverter topology for 3-level
inversion

S11
S21
S31
C1
S22
S12
S32

Vdc
o
C
A
B
3-ph Ac mains
C2
S13
S23
S33
S14
_
S24
S34

• The neutral point fluctuates as the capacitors
  C1 and C2 carry load currents
• Bulkier capacitors are needed to check the
  neutral point fluctuation
• PWM strategies aim to balance the neutral point
  dynamically

10
Dual Inverter fed induction motor with open end
winding
11
Dual Inverter fed induction motor with open end
winding
Inverter-II
Inverter-I
Vdc/4
a
o
a
b
b
c
c
Vdc/4
3-ph IM with open wdg.

• The neutral point of the conventional IM is
  opened and is fed from both sides.
• The DC - bus voltage is Vdc/2 .

12
Space phasor locations for Inverter-I (Left) and
Inverter-II (Right)
13
Voltage space phasor combinations from the dual
inverter scheme

• A total of 64 space phasor combinations are
  available

14
Dual Inverter fed induction motor with open end
winding with isolated DC power supply
a
a
Vdc/2
Vdc/2
b
b
c
c
IM with open-end winding
Inverter - 2
Inverter - 1

• Triplen harmonic suppression is achieved through
  the transformer isolation.

15
A new three-level inverter circuit topology
cascading two two-level inverters
16
The power circuit configuration of a three-level
inverter cascading conventional two two-level
inverters
17
Space vector locations of the proposed
three-level inverter
Similar to the conventional three-level inverter
18
Salient features of the proposed three-level
inverter configuration

• The power Bus structure is simple
• Can work as a conventional 2-level inverter in
  the lower voltage range
• The total VA rating of the the transformers is
  the same as that of the NPC configuration
• High voltage fast recovery diodes are not needed
• Three devices need to support the total DC bus
  voltage

19
Experimental results lower modulation range
A1
Vdc/2 150V
Vdc/2 150V
A2
O
20
Experimental results higher modulation range
21
Experimental results over modulation range
Phase voltage
Pole Voltage waveforms of Inverter-1 (Top) and
Inverter-2 (Bottom)
Vsr Vdc (Over-modulation)
Phase current at no-load
22
A new five-level inverter circuit topology
cascading two three-level inverters
23
Introduction

• An inverter system for open-end winding induction
  motor is presented.
• Open-end winding IM is fed by two three-level
  inverters
• The 3-level inverters are realised by cascading
  two 2-level inverters
• This inverter scheme results in space phasor
  locations similar to a conventional Five-level
  Inverter

24
The schematic for the proposed five-level drive

• Inverter A and Inverter B are 3-level inverters
• Each three level is formed by cascading two
  2-level inverters

25
The 3-level inverter topology

• The 2-level inverters have DC-link of
• This 3-level structure does not require neutral
  point clamping diodes

Vdc/4
26
Realization of five voltage levels across motor
phases

• All legs of the three-level inverter can
  independently take any of the three levels
• when inverter-A and inverter-B are switched
  independently 5-levels can be generated across
  the winding.

for the first three levels only Inverter-B is
switching
27
Space vector representation of the proposed Drive

• Similar to a five-level inverter
• 125 space vector combinations
• 96 sectors
• 61 locations
• Four layers

28
The Modulation scheme
Multi-carrier PWM method is used Four triangular
carriers 20 third harmonic added to the 3
reference signals A discreet DC shift is given
to the reference signals depending on the speed
range With this modulating scheme the inverter
starts with 2-level operation and then moves to
3-level, 4-level and 5-level operation as speed
increases
29
Conventional SPWM For Low modulation index

• The reference wave set is placed at
• the middle of the carrier set
• Three levels are involved, therefore
• three-level waveform

SPWM for the proposed Drive

• The reference wave set is placed at
• the middle of the lowermost carrier
• Only two levels are involved, therefore
• two-level waveform
• Only INV3 is switching ( the top
• 2-level inverter of Inverter-B)
• hence losses are only due to INV3

30
Conventional SPWM
For next speed range (Vc /2lt
Vm ltVc ) Vc Peak to peak amplitude of the
carrier Vm Peak amplitude of the reference
wave
SPWM for the proposed Drive

• The reference wave set is placed at
• the middle of the lower two carriers
• Three levels are involved, therefore
• three-level waveform
• Only INV4 and INV3 are switching
• (2-level inverters of Inverter-B)
• losses are only due to Inverter-B

31
For next speed range
(Vc ltVmlt3Vc/2 )
Conventional SPWM

• Five levels are involved, therefore
• five-level waveform
• All the 2-level inverters have to
• be switched

SPWM for the proposed Drive

• The reference wave set is placed at
• the middle of second carrier ( C2)
• Four levels are involved,
• therefore four-level waveform
• Only INV2, INV4 and INV3 are
• switching
• INV1 is not switching

32
For the maximum speed range ( Vmgt 3Vc/2 )

• The reference set is at the center of the carrier
  set
• All the Five-levels are involved
• All the inverters have to be switched

33
2-Level operation

• Phase voltage shows 2-level waveform

Motor phase voltage during 2-level operation

• Inverter-B,is switching between Vdc/2 and Vdc/4
  ( 200V and 100V)
• This is due to the switching of INV3 ( top
  inverter of Inverter-B). INV4 is clamped.

Pole voltage of Inverter-B during 2-level
operation

• Inverter-A is clamped to zero

Pole voltage of Inverter-A during 2-level
operation
34
3-Level operation

• Motor Phase Voltage shows 3-level waveform

• Inverter-B is switching as 3-level inverter
  (200V,100V,0V)
• Both the 2-level inverters of Inverter-B ( INV3
  and INV4 are switching)
• Inverter-A still clamped to zero

Motor phase voltage during 3-level operation
Pole voltage of Inverter-B during 3-level
operation
35
4-Level operation

• Motor Phase Voltage shows 4-level waveform

Motor phase voltage during 4-level operation

• Inverter-B is switching as 3-level inverter
  (200V,100V,0V)

• Inverter-A is switching as 2-level inverter
  (100V,0V)
• This is due to the switching of INV2( bottom
  2-level inverter )

Pole voltage of Inverter-B
Pole voltage of Inverter-A
36
5-Level operation

• Motor Phase Voltage shows 5-level waveform

• Inverter-B is switching as 3-level inverter
  (200V,100V,0V)

Motor phase voltage during 5-level operation

• Inverter-A is also switching as 3-level
  inverter (200V,100V,0V)

Pole voltages of Inverter-A (top) and
Inverter B (bottom) experimental results
Pole voltages of Inverter-A and Inverter
B Showing the phase relation (simulation results)
37
Motor phase current
2-level operation
3-level operation
4-level operation
5-level operation
38
Salient Features
Feeding the open-end winding induction motor by
3-level inverters, results in voltage space
phasors similar to a 5-level inverter
The three level inverters used are realised by
cascading Two 2-level inverters. This structure
does not require neutral Clamping diodes .
Compared with series connected H-bridge topology,
the proposed drive scheme uses less number of
power Supplies ( four against six required for
H-bridge).
39
Open end winding IM drive (Three level operation)
with a single DC link
40
Dual Inverter fed induction motor with open end
winding with isolated DC power supply
a
a
Vdc/2
Vdc/2
b
b
c
c
IM with open-end winding
Inverter - 2
Inverter - 1

• Triplen harmonic suppression is achieved through
  the transformer isolation.
• All the 64 - space phasor combinations can be
  used in this case.
• The transformers are bulky and expensive.

41
Triplen harmonic contribution from various
space- vector combinations (Twenty combinations
are available with a triplen harmonic content of
zero)
42
Space phasor combinations with zero triplen
harmonic contribution
43
Proposed power circuit schematic (switched
neutral)

• Auxiliary switches SW 1 and SW 3 are opened when
  inverter-1 assume states 7 or 8.( switched
  neutral)
• Auxiliary switches SW 2 and SW 4 are opened
  when inverter-2 assume states 7 or 8.
• For safe combinations auxiliary switches are
  kept closed.

44
Title

• Space phasor combinations used in the proposed
  control strategy
• Space phasor locations G,I,K,M,P,Q and R are
  forbidden.
• For combinations at H,J,L,N,Q and S the
  auxiliary switches need not be opened ( safe
  states).
• Other combinations have a zero state at one end.
  Appropriate auxiliary switches are opened to
  achieve triplen harmonic suppression

45
Experimental results
46
Experimental results
Pole voltages of individual inverters and the
phase voltage (middle) with triplen content when
Vsr 0.6Vdc
Actual motor phase voltage (left) and the motor
phase current (right) when Vsr 0.6Vdc
47
Experimental results
Pole voltages of individual inverters and the
phase voltage (middle) with triplen content when
Vsr 0.9Vdc
Actual motor phase voltage (left) and the motor
phase current (right) when Vsr 0.9Vdc
48
A Dual Two Level Inverter Scheme for an Open-end
winding Induction Motor Drive with a Single DC
Power Supply and improved DC bus Utilization
49
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50
Salient features of the switching strategy

• The triplen harmonic currents are denied a path
  by turning off the auxiliary switches.
• The auxiliary switch pairs toggle in this
  switching strategy with a fixed frequency.
• At a time only one inverter is connected to the
  DC link
• The DC-bus utilization is enhanced by about 15
  compared to the earlier switching strategy.

51
(No Transcript)
52
Experimental results
The motor phase voltage
The motor phase current
Vsr 0.4Vdc
53
Experimental results
The triplen harmonic voltage in (vAO
- vAO)
Top trace Voltage across the auxiliary
switch Bottom trace Current through the
auxiliary switch
Vsr 0.4Vdc
54
Experimental results three-level operation
55
Experimental results over modulation operation
56
Experimental results
57
Multi-level structures with asymmetric DC link
voltages
58
A Multilevel Voltage Space vector Generation for
an Open-end winding Induction Motor Drive using a
dual-inverter scheme with Asymmetrical DC-link
voltages
59
Salient features of the proposed Drive

• A dual-inverter fed open-end winding IM drive is
  proposed, with asymmetric
• DC-link voltages (in the ratio 21).
• In this scheme, 64 space vector combinations are
  distributed over 37 space vector
• locations with 54 sectors.
• The switching ripple is lesser compared to the
  earlier scheme i.e. with
• equal DC-link voltages.
• The motor phase voltage waveform exhibits either
  2-level waveform,
• 3-level waveform or the 4-level waveform
  depending upon the motor speed.

60
Dual Inverter fed induction motor with open end
winding with asymmetric voltages showing
individual space phasor combinations
a
a
1/3Vdc
2/3Vdc
b
b
c
c


IM with open-end winding
Inverter - 1
Inverter - 2
(- - ) 3
2 ( - )
(- - ) 3
2 ( - )
( - ) 4
1 (- -)
( - ) 4
() 7
8 (- - -)
1 (- -)
8 (- - -)
() 7
6 ( - )
( - - ) 5
( - - ) 5
6 ( - )
2 / 3 Vdc
1 / 3 Vdc
61
Space phasor combinations for asymmetrical
voltage dual - inverter drive

• 64 space vector combinations
• 54 sectors
• 37 locations
• three layers

62
Experimental results
Motor phase voltage (left) and the motor phase
current (right) when Vsr 0.2Vdc (2-level
waveform)
Normalized harmonic spectrum of the motor phase
voltage illustrating the absence of the triplen
-harmonic content for Vsr 0.2Vdc
63
Experimental results
64
Experimental results
65
Experimental results
The actual motor phase voltage and motor phase
current when Vsr Vdc
The harmonic spectrum of the motor phase voltage
(showing the absence of the triplen harmonic
content) for Vsr Vdc
66
Experimental results
The actual motor phase voltage and motor phase
current during square wave ( 18 - step
operation)
Normalized harmonic spectrum of the motor phase
voltage illustrating the absence of the triplen
-harmonic content for 18-step operation
67
A Multilevel Inverter System for an Open-end
Winding Induction Motor
68
The salient features of the proposed scheme

• In the proposed scheme, a total of 512 voltage
  space vector combinations are present,
  distributed over 91 space vector locations.
• The three-level inverter in this scheme is
  realized by cascading two two-level inverters.
• In the lowest speed range, only one of the three
  inverters is switched. In the medium speed range
  two inverters are switched and in the higher
  speed range, all the three inverters are
  switched.
• This feature ensures that the switching losses
  are reduced in the lower and the middle range of
  speed.
• The motor phase voltage shows a 2-level waveform
  in the lowest speed range, a 3-level or a 4-level
  waveform in the medium speed range, a 5-level or
  a 6-level waveform in the higher speed range.
• This configuration needs three isolated power
  supplies.

69
Schematic circuit diagram of the proposed
inverter scheme
70
Space vector locations from the individual
inverter structures

• In the lower speed range, only inverter-3 is
  switched (2-level waveform)
• In the medium speed range Inverter-2 and
  Inverter-3 are switched (3-level or 4-level
  waveforms)
• In the higher speed range, all the inverters are
  switched. ( 5-level or 6-level waveform)

71
Combined space vector locations (inner layers)
Resultant space vector locations when inverter-1
is inactive i.e. clamped to the state 8(---)
72
Combined space vector locations (outer layers)
73
Title
74
Experimental results
75
Experimental results
Motor phase current at no-load
Motor phase voltage
Vsr 0.65Vdc (Layer-4)
Motor phase current at no-load
Motor phase voltage
Vsr 0.83Vdc (Layer-5)

• All the three inverters are switched in these
  two layers

76
Experimental results
77
Seven-level voltage space phasor generation
scheme for an open-end winding induction motor
drive with asymmetric dc link voltages
78
Multi-level inverter configuration for induction
motor with open-end winding structure with
asymmetric DC Links
-
-

• Higher-level voltage waveforms can be synthesized
  when individual inverters are supplied with
  unequal DC link voltages
• Seven-level space phasor generation from a
  five-level inverter
• DC link voltage of the top two-level inverters is
  Vdc/3
• DC link voltage of the bottom two-level inverters
  is Vdc/6

79
Multi-level inverter configuration for induction
motor with open-end winding structure with
asymmetric DC Links
-
-

• Requires only four isolated power supplies

80
Seven-level inverter configuration with
asymmetric dc link voltages
81
Seven-level voltage space phasor generation
82
Space vector diagram of seven-level inverter
343 space vector combinations 127 space
vector locations 216 triangular
sectors
83
Seven-level voltage space phasor generation scheme
Comparison proposed inverter scheme
with H-bridge inverter configurations
84
Space vector diagram of seven-level inverter
164
172
168
170
162
166
163
165
161
173
171
167
169

• 216 sectors
• 6 layers
• Over-modulation

106
110
112
108
174
114
160
113
115
111
159
105
107
109
175
68
64
66
116
158
104
62
176
117
65
67
69
177
61
157
63
103
178
30
32
60
156
102
118
70
34
31
33
35
59
71
119
179
29
155
101
10
12
58
180
28
36
72
100
120
154
73
153
9
11
37
99
121
13
27
57
181
74
2
56
14
152
122
8
38
98
182
26
183
39
123
1
3
7
25
55
75
151
97
15
16
184
24
150
76
216
124
4
6
40
96
54
17
23
215
125
5
53
77
95
149
185
41
214
42
186
18
22
52
148
126
20
78
94
93
21
51
213
187
19
79
147
127
43
92
44
212
146
188
46
50
128
81
48
45
145
211
49
91
129
189
47
81
90
210
84
86
130
82
144
88
190
143
83
87
131
85
191
89
29
In V/f mode, the length of the reference space
vector is decided by the speed command.
138
132
208
192
136
140
134
142
133
139
135
137
207
193
141
206
194
196
1989
200
202
204
195
197
205
203
199
201
85
Phase-A voltage, phase-A current and common mode
voltage waveforms for M.I. 0.14 (Layer 1
operation)
VA2A4
IA
VOO
86
Phase-A voltage, phase-A current and common mode
voltage waveforms for M.I. 0.28 (Layer 2
operation)
VA2A4
IA
VOO
87
Phase-A voltage, phase-A current and common mode
voltage waveforms M.I. 0. 43 (Layer 3 operation)
VA2A4
IA
VOO
88
Phase-A voltage, phase-A current and common mode
voltage waveforms for modulation index 0.57
(Layer 4 operation)
VA2A4
IA
VOO
89
Phase-A voltage, phase-A current and common mode
voltage waveforms for modulation index 0.72
(Layer 5 operation)
VA2A4
IA
VOO
90
Phase-A voltage, phase-A current and common mode
voltage waveforms for modulation index 0.84
(Layer 6 operation)
VA2A4
IA
VOO
91
Phase-A voltage and phase-A current waveforms for
modulation index 0.94 (over- modulation
operation)
VA2A4
IA
92
Phase-A voltage and phase-A current waveforms for
36-step mode
VA2A4
IA
93
Inverter operation under speed reversal- Phase-A
voltage and phase-A current
VA2A4
IA
94
A High-Resolution Multi-Level Voltage Space
Phasor Generation for an Open-end Winding
Induction Motor Drive
95
Introduction

• A topology for high resolution voltage space
  phasor generation
• for an open-end winding induction motor drive
  is presented

• The open-end winding induction motor is fed
  from both ends
• by two 3-level inverters with asymmetrical
  DC links

• This results in voltage space phasors
  equivalent to
• a conventional 9-level inverter

• The 3-level inverters used in the proposed
  drive, are realised
• by cascading two 2-level inverters

96
The power Circuit
Inverter A
Inverter B
INV 1
INV 3
S13
S15
S11
S35
S33
S31
3/8Vdc
C1
C3
C3
A1
B1
C1
B3
A3
S32
S36
S34

• Inverter A and
• Inverter B are
• 3-level inverters

S16
S12
S14
-
S25
S23
S21
S43

S45
S41
C2
C4
C4
C2
B2
B4
3/8Vdc
A2
A4
S22
S26
S24
S42
S46
S44
-
INV 2
INV 4
O
O
97
The levels across the machine phase winding
Inverter A Levels in A-leg ( VA2O )
Inverter B Levels in A-leg ( VA4O )
Levels in A-phase of the machine ( VAA VA2O
- VA4O)
2/8 1/8 0 2/8 1/8 0 2/8 1/8 0
0 0 0 3/8 3/8 3/8 6/8 6/8 6/8
-2/8 L1 -1/8 L2 0 L3 1/8 L4 2/8 L5 3/8 L6
4/8 L7 5/8 L8 6/8 L9
98
Space vector representation
217 Locations 384 Sectors
9-levels in space vector Amplitudes along
0,1/8, Vdc,2/8 Vdc, 3/8 Vdc ,4/8 Vdc , 5/8
Vdc , 6/8 Vdc , 7/8 Vdc and Vdc
99
Conventional SPWM
For Low modulation index

• The reference wave set is placed at
• the middle of the carrier set
• Three levels are involved, therefore
• three-level waveform

SPWM for the proposed Drive

• The reference wave set is placed at
• the middle of the lowermost carrier
• Only two levels are involved, therefore
• two-level waveform
• Only INV3 is switching ( the top
• 2-level inverter of Inverter-B)
• hence losses are only due to INV3

100

• A progressive discreet DC shift in steps of
  Vc/2 is
• given to the reference wave set as the speed
  increases

• The inverter then moves through
  3-level,4-level,5-level,
• 6-level,7-level,8-level and 9-level operation

9-level operation for the maximum speed range
101
Experimental results
INV1 and INV2 DC-link 150V ( 3/8 Vdc)
INV3
and INV4 DC-link 50V ( 1/8 Vdc) Layer 1
Phase voltage 2-level waveform
Only INV3 of Inverter-B is switching in 2-level
mode ( 100 V and 50V)
Pole voltage of Inverter-B
102
Experimental results -Layer 2
Phase voltage 3-level waveform
Inverter-B in 3-level operation Inverter-A not
switching ( 100V, 50V and 0V)
103
Experimental results -Layer 3
Phase voltage 4-level waveform
Inverter-B in 3-level operation
Inverter-A starts switching in 2-level mode (
100V and 0V)
104
Experimental results -Layer 6
Phase voltage 7-level waveform
Inverter-A in 2-level operation
Inverter-B in 3-level mode
105
Experimental results -Max speed range
Phase voltage 9-level waveform
Inverter-A also in 3-level operation (
300V,150V,0V)
Inverter-B in 3-level mode ( 100V,50V,0V)
Inverter-A switching less frequently than
Inverter-B
106
The Current waveforms
During 8-level operation
During 9-level operation
The Harmonic Spectrum of the Phase Voltage
During 9-level operation
107
Common mode voltages and its effect on induction
motor drive operation
108
Common-mode Voltage Generation by a Multi-level
VSI

S21
S11
S31
C1
S22
S12
S32
o
Vdc
C
B
A
b1
a1
c1
C2
S13
S23
S33
Induction Motor
_
S14
S24
S34
N
109
Three-level inverter configuration with common
mode voltage elimination
110
Common mode voltages and its effects

• PWM inverters generate high frequency, high
  amplitude common mode voltages, which induces
  shaft voltage on the rotor side
• When the induced shaft voltage exceeds the
  breakdown voltage of the lubricant in the
  bearings, result in large bearing currents
• Problems associated erosion of the bearing
  material, premature mechanical failure of
  bearings leading to motor failure, increase in
  total leakage current through the ground
  conductor resulting into increased conducted EMI
  and false tripping of relays
• PWM inverters which do not generate common mode
  voltage are suggested as a solution to the above
  problems

111
Three-level inverter configuration with common
mode voltage elimination
112
A dual two-level inverter scheme with common mode
voltage elimination for an induction motor drive
113
Schematic of dual inverter fed open end winding
induction motor drive with isolated DC-links
114
The voltage space vectors of the individual
inverters
B
B
C
C
3
2
2
3
A
A
D
D
4
O
O
4
1
1
5
E
6
F
E
F
INV2
5
6
INV1
Magnitude of space Phasors
115
The voltage space vectors and space phasor
combinations of the dual inverter
36
25
J
I
K
26
35
37
27
15
34
75
76
46
21
L
H
B
C
86
16
85
45
28
38
24
31
41
77
47
17
14
18
81
74
71
11, 33
22,44
D
M
O
G
A
87,78
48
65
56
74
55,66
A -phase axis
88
32
23
73
82
42
13
72
54
43
67
E
F
N
S
51
64
57
61
68
12
58
83
62
53
P
52
R
63
Q
116
Voltage space vector combinations producing zero
common mode voltage in the motor phase windings
117
Schematic of dual inverter fed open end winding
induction motor drive with single DC-links
118
Voltage vectors without triplen contribution
J
I
K
26
35
H
2
L
46
15
3
31
24
22
33
M
1
G
O
4
11
44
A -phase axis
66
55
77
88
13
42
N
S
51
64
5
6
62
53
P
R
Q
119
The space phasor combinations for active vectors
and zero vectors used in the present work (for
sequence-1)
35
J
I
K
31
15
H
2
L
3
33
55
M
1
G
11
O
11
4
A -phase axis
55
33
51
N
S
13
5
6
P
R
Q
53
120
The reference space phasor Vsr for the dual
inverter
35
J
I
K
31
15
H
2
L
3
33
55
G
M
11
O
11
4
1
A -phase axis
55
33
5
51
N
S
13
6
P
R
Q
53
121
Experimental results lower speed range
Pole voltage and its FFT
Phase voltage and its FFT
122
Experimental results higher speed range
Pole voltage and its FFT
Phase voltage and its FFT
123
Three-level inverter configuration with common
mode voltage elimination for an induction motor
drive
124
Three-level inverter configuration with common
mode voltage elimination

• A three level inverter scheme based on open-end
  winding configuration is proposed, which, uses
  only half the DC link voltage, compared to the
  scheme based on conventional NPC inverter
• The proposed scheme generates the three-level
  voltage waveforms across the motor phases with
• Zero common mode voltage in the motor phase
  voltage
• Zero common mode voltage in the pole voltage

125
The five-level inverter configuration
126
space vector combinations for inverter-A ,
inverter-B
B axis
0-
--
-
00- 0
-0- 00
0-
-0
A axis
000 ---
0-- 00
-00 0
-
--
0-0 0
--0 00
-0
-0
--
0-
-
C axis
Vdc /2
127
Five-level Inverter voltage space vector
representation
B-phase Axis
Shaded inverter voltage space phasor locations
produce zero common mode voltage in the phase
voltage of IM
42
43
44
45
46
62
64
66
68
61
63
65
67
69
23
24
25
26
41
47
30
32
34
60
70
29
31
33
35
71
59
22
48
11
12
10
27
40
28
36
72
10
12
58
27
73
9
11
13
37
57
49
3
4
9
13
21
28
39
26
74
2
8
14
38
56
7
25
39
1
3
15
55
75
1
29
2
5
8
14
20
38
50
6
16
24
40
54
76
96
4
23
5
17
41
53
77
95
30
A-phase Axis
6
7
15
19
37
51
61
20
22
42
52
78
94
18
51
19
21
43
79
93
17
18
31
16
36
52
60
44
46
48
50
81
92
45
47
49
81
91
32
33
34
35
59
53
84
86
88
90
82
83
85
87
89
54
56
57
58
55
C-phase Axis
Vdc
128
Inverter voltage space phasor locations with zero
common mode voltage in the phase voltage of IM
B-phase Axis
I
H
J
K
B
G
A
C
A- phase axis
0
L
R
D
F
E
M
Q
N
P
Vdc
O
C-phase Axis
129
Three-level inverter configuration with common
mode voltage elimination
Classification of inverter voltage vectors of
three-level inverters
130
Voltage space vectors of inverter-A (belonging to
group C, D and E) in a three dimensional plane
a-ß-0 plane
Vcm1
Group C
0
Group D
00-
Group E
-00
0-0
131
The resultant three-level space vector
configuration when group D switching states are
used to switch inverters-A and inverter-B
132
Inverter configuration with common mode voltage
elimination
133
Three-level inverter configuration with common
mode voltage elimination
Salient Features

• A three-level inverter configuration with common
  mode elimination
• is proposed for an induction motor drive
  with open-end windings.
• Common mode voltage generated across the motor
  phases is zero.
• Suppresses the common mode currents which
  otherwise will flow
• in the machine windings.
• Common mode voltage in the inverter pole voltage
  is zero.
• The problems associated with the common mode
  voltages inducing
• currents in the leakage capacitances are
  completely eliminated (as
• the electrostatic coupling between stator
  winding to stator iron and
• between stator winding and rotor iron is
  ineffective)
• Only two power supplies are required whereas the
  equivalent
• three-level inverter configuration with
  common mode elimination
• based on H-bridge topology requires six
  isolated power supplies.
• DC link voltage requirement is only half to that
  of the conventional
• three-level inverter configuration with
  common mode elimination.

134
Output vectors selected for inverter switching
B-phase Axis
A phase axis
1
Vdc
C-phase Axis
135
Pole voltage waveforms for modulation index 0.4
(Layer 1 operation) and its FFT
136
Phase-A voltage and phase-A current waveform for
modulation index 0.4 and FFT of phase voltage
(Layer 1)
137
Pole voltage waveforms for modulation index 0.7
(Layer 2 operation) and its FFT
138
Phase-A voltage and phase-A current waveform for
modulation index 0.7 and FFT of phase voltage
(Layer 2)
139
Pole voltage waveforms for modulation index 0.95
(over-modulation operation) and its FFT
140
Phase-A voltage and phase-A current waveform for
modulation index 0.95 and FFT of phase voltage
141
Pole voltage waveforms for twelve-step mode and
its FFT
142
Phase-A voltage and phase-A current waveform for
twelve-step mode and FFT of phase voltage
143
Five-level inverter configuration with common
mode voltage elimination for an induction motor
drive
144
Power Scheme of One Leg of Proposed Five-level
Inverter by Cascading Conventional Two-level and
Three-level VSIs
IGBT Gating Logic
1 ? ON, 0 ? OFF S11-S14, S21-S34, S24-S31,
and S41-S44 are complementary pairs of switches
145
Power Schematic for The Nine-level Inverter
Configuration
146
Switching States and Voltage Space Vector
Locations of Inverter-A (a Five-level Inverter)
96 Sectors 61 Vectors 125 Switching States
147
Groups of Common-mode Voltage Generated by
Individual Five-level Inverter
148
Groups of Switching States and Amplitude of
Resulting Common-mode Voltage in Five-level
Inverter (Inverter-A and Inverter-A)
149
Voltage Vector With Corresponding Switching State
Resulting Zero Common-mode Voltage in Five-level
Inverter (Inv.-A and Inv.-A)
24 Sectors 19 Vectors 19 Switching States
150
Combined Voltage Space Vector Locations of a Dual
Five-level Inverter Fed Open-end Winding IM Drive
(a Nine-level Inverter)
384 Sectors 217 Vectors 15,625 Switching States
151
Number of Redundant Switching States Available
for Voltage Vectors of Five-level Inverter with
Zero Common-mode Voltage
96 Sectors 61 Vectors 361 Switching States
152
Switching State Combination Selected to Generate
The Voltage Space Phasors of Five-level Inverter
With Zero CMV
96 Sectors 61 Vectors 61 Switching States
153
Power Scheme of Proposed Five-level Inverter With
CME
154
Experimental results
Two-level operation m0.2
Pole voltage spectrum
Phase voltage spectrum
155
Experimental results
Three-level operation m0.33
Pole voltage spectrum
Phase voltage spectrum
156
Experimental results
Four-level operation m0.6
Pole voltage spectrum
Phase voltage spectrum
157
Experimental results
Five-level operation m0.72
Pole voltage spectrum
Phase voltage spectrum
158
Experimental results
Over modulation m0.97
Pole voltage spectrum
Phase voltage spectrum
159
Experimental results
Four-level operation m0.6
Five-level operation m 0.72
Over modulation m 0.97
160
Three-level inverter scheme with common
mode voltage elimination and dc-link capacitor
voltage balancing for an open end winding
induction motor drive
161
Power schematic of a three-level inverter with
common-mode voltage elimination

• Each side on motor is fed with three-level
  inverters
• Requires half the DC link voltage, compared to
  the scheme based on conventional NPC inverter

• The proposed scheme generates the three-level
  voltage waveforms across the motor phases with
• Zero common mode voltage in the motor phase
  voltage
• Zero common mode voltage in the pole voltage

162
Three-level inverter with common-mode voltage
elimination
Salient Features

• Multiplicity of inverter vector locations has
  been effectively utilized to arrive at a DC Link
  capacitor voltage-balancing scheme
• The proposed capacitor voltage-balancing scheme
  is implemented without compromising on the SVPWM
  scheme and a simple hysteresis controller can be
  used to balance the DC link capacitor voltages
• Requires only one isolated passive front-end
  power supply

163
The switching combinations for three-level
inverter with common mode voltage elimination

• Proposed scheme generates the three-level voltage
  waveforms across the motor phases with
• Zero common mode voltage in the motor phase
  voltage
• Zero common mode voltage in the pole voltage
• The DC Link voltage is half as compared to the
  three-level NPC inverter

Switching combination 0-, -0 means inverter-A
state is 0- inverter-B state is -0
164
Inverter-induction motor system model

• Each leg of individual three-level inverter is
  modeled as a three pole switch

1 gt - Vdc/2 2 gt 0 3 gt Vdc/2

• Switching function
• S 1 if switch is connected to -Vdc/2
• 2 if switch is connected to 0
• 3 if switch is connected to Vdc/2

165
Inverter-induction motor system model

• Source current iS
• Currents drawn from DC link- i1, i2, i3
• Inverter-A currents -i1A,i2A,i3A, Inverter-A
  currents -i1B,i2B,i3B
• Induction motor currents- ia, ib, ic

166
Analysis of DC link capacitor voltage unbalance
for proposed three-level inverter configuration
The inverter pole voltages with respect to
negative DC rail, in terms of capacitor voltages
167
Analysis of DC link capacitor voltage unbalance
for proposed three-level inverter configuration
The currents drawn from the DC Link nodes
(i1,i2,i3) in terms of motor currents (ia, ib, ic)
Inverter-A
Inverter-B
Motor currents
Motor currents
168
Analysis of DC link capacitor voltage unbalance
for proposed three-level inverter configuration
The current drawn from the middle point on the DC
link is responsible for unbalance
169
Classification of the inverter voltage vectors

• Classification is based on
• Voltage produced in the output
• Connection of IM phase winding to the Capacitors

• LV Large Voltage Vectors
• ZV Zero Voltage Vectors
• SV Small Voltage vectors
• MV Medium Voltage vectors

170
Large Voltage Vectors (LV) and their effect on DC
link capacitor voltages

• Two windings directly across full DC link
• One winding short circuited at middle DC link
  point
• No effect on capacitor voltages as load current
  is drawn directly from source

C2
B
A
C
C1
G (0-, -0)
171
Middle Voltage Vectors (MV) and their effect on
DC link capacitor voltages

• One winding directly across full DC link
• One windings across each capacitor
• The difference between these two winding currents
  is drawn through the mid-point of DC link
• Has unbalancing effect on capacitor voltages

C2
C2
B
A
C
C
A
B
C1
C1
0- , 0-
0- , -0
(b)
(a)

• Each MV vector location has two switching
  combinations
• The IM phase windings are connected to opposite
  capacitors in these two combinations
• Ex vector location H
• (a) 0-,-0 A phase bottom capacitor and B phase
  top capacitor
• (b) 0-,-0 A phase top capacitor and B phase
  bottom capacitor

172
Space vector combinations and their effect on DC
link capacitor voltages inverter vector location
A (Small Voltage vector)
One winding across each capacitor
One winding across each capacitor
B
C
A
NSV
NSV
(a) 000,-0
Normal Small Voltage Vector
Normal Small Voltage Vector
Two windings across TOP capacitor
Two windings across BOTTOM capacitor
USV
LSV
Upper Small Voltage Vector
Lower Small Voltage Vector
173
Summary Classification of switching combinations
of proposed inverter voltage vector locations
LV Large Voltage Vectors ZV Zero Voltage
Vectors MV Medium Voltage vectors USV Upper
Small Voltage vectors NSV Normal Small Voltage
vectors LSV Lower Small Voltage vectors
174
DC link capacitor voltage balancing scheme for
the proposed three-level inverter fed induction
motor drive

• ZV and LV do not have any unbalancing effect on
  the DC link capacitor voltages
• MV and NSV group generate very low voltage
  unbalance. Each have two switching combinations
  with phase windings EXCHANGING their connections
  to DC link capacitors.
• Thus, effect of one switching combination on the
  capacitor voltages is nullified by another
  switching combination
• Alternate switching of NSV and MV switching
  combinations in consecutive sampling durations
  will maintain the capacitor voltages balanced.

• Thus inverter voltage vectors belonging to ZV,
  NSV, MV and LV can be used effectively to
  maintain the voltage balance across the DC Link
  capacitors
• No voltage/current feedback required
• Works on alternate switching of NSV and MV
  switching combinations

175
The sequence of various switching combinations
during POS_SEQ and NEG_SEQ
TS
TS
high
low
176
Sector formed by inverter voltage vectors
A-G-R
I

• Alternate switching combinations are selected for
  A (NSV) and R(MV) inverter voltage vectors in
  the consecutive sampling interval
• The capacitor voltage unbalance in sampling
  interval POS_SEQ is nullified in next sampling
  interval NEG_SEQ

J
H
K
B
G
Y
A
C
R
0
L
D
F
Q
Q
M
E
P
N
O
A
G
R
A
G
A
R
A
0-, -0
000, -0
0-, 000
000, -0
0-, 000
0-, -0
0-, -0
-0, -0
TS
TS
high
POS_SEQ
NEG_SEQ
2TS
low
TS
177
Sector formed by inverter voltage vectors 0-A-B
I

• Alternate switching combinations are selected for
  A (NSV) and B(NSV) inverter voltage vectors in
  the consecutive sampling interval
• The capacitor voltage unbalance in sampling
  interval POS_SEQ is nullified in next sampling
  interval NEG_SEQ

J
H
K
B
G
Y
A
C
R
0
L
D
F
Q
Q
M
E
P
N
O
0
A
B
0
A
0
B
0
0- , 000
000, 000
000, 000
000,000
000, 0-
000, -0
000, 000
0-, 000
TS
TS
high
POS_SEQ
NEG_SEQ
2TS
low
TS
178
Open loop DC Link capacitor voltage balancing
scheme
179
Open loop DC Link capacitor voltage balancing
controller (Simulation results)
DC Link Voltage
Capacitor voltages
180
Deviation in the capacitor voltages when the open
loop DC Link balancing controller is turned off
(Simulation results).
DC Link Voltage
Capacitor voltages
181
Harmonic frequency distribution of phase voltages
for balanced and unbalanced capacitor voltage
conditions
Low order even harmonics causes damaging effects
to the machine because of the current harmonics
resulting in torque pulsations and increased
machine losses
182
Open loop DC Link capacitor voltage balancing
scheme

• Disadvantage Gradual drift in the capacitor
  voltages in the open loop scheme
• Possible Reasons
• Use of the asynchronous PWM,
• Unequal time durations of the MV and NSV inverter
  vectors in consecutive switching intervals
• Unbalanced load currents etc

sec
183
Hysteresis controller based closed loop DC Link
balancing scheme

• Switching combinations from USV charge lower
  capacitor and discharge upper capacitor
• Switching combinations from LSV discharge lower
  capacitor and charge upper capacitor
• USV and LSV group switching combinations are used
  to balance the capacitor voltages

• Hysteresis controller selects the LSV or USV
  group instead of NSV depending upon the
  difference in the capacitor voltages, ?vC
• Closed loop scheme involves sensing the capacitor
  voltages

184
Hysteresis controller based closed loop DC Link
balancing scheme
185
Operation of closed loop controller for DC link
balancing (Simulation results)
Capacitor voltages
?vC
Controller output state
186
The deviation in the capacitor voltages when the
DC Link voltage-balancing scheme is turned off
for a small interval
187
DC Link voltage-balancing scheme in 12-step mode

• SV are not switched for longer duration in the
  12-step mode
• Capacitor voltages deviate from the balanced state

188
DC Link voltage-balancing scheme in 12-step mode
Slight reduction in the modulation index restores
the capacitor voltages to balanced state in
12-step mode
189
Experimental Results
190
Balancing of DC link capacitor voltages VC1 and
VC2 during steady state operation
VC1,
VC2
191
Balancing of the DC Link capacitor voltages after
the controller is disabled for small interval,
inner layer operation
VC1
VC2
192
Balancing of the DC Link capacitor voltages after
the controller is disabled for small interval,
outer layer operation
VC1
VC2
193
The DC link voltages and machine phase current
under while machine operating in inner layer is
accelerated to outer-layer and then to
over-modulation
Phase current
VC1,
VC2
194
The DC link voltages and machine phase current
under while machine operating in inner layer is
subjected to speed reversal
Phase current
VC1,
VC2
195
Space vector PWM signal generation for
multi-level inverters using only the sampled
amplitudes of reference phase voltages
196
Space vector PWM signal generation for
multi-level inverters using only the sampled
amplitudes of reference phase voltages
Conventional Space Vector Based PWM

• Identify the sector
• Determine the timings
• Determine the Actual vectors
• Generate the Gate signals

Sector Identification a. With Angle and
magnitude information b. Using level
comparators
Timing a. Direct equations b.
Mapping the sector to an appropriate inner sector
197
Space vector PWM signal generation for
multi-level inverters using only the sampled
amplitudes of reference phase voltages
In the Proposed Work

• Sector identification is not required
• No need to compute switching times for each
  vector
• Does not use look-up tables to select vectors
• The inverter leg switching times are directly
  obtained with a simple
• algorithm using only the sampled
  amplitudes of the reference
• phase voltages

• Faster computations
• Generate the inverter gate signals for the
  entire modulation range extending up to six step
  mode

198
Two level SVPWM
199
Offset voltage determination for Two level SVPWM

• Addition of Voffset1 centers the active inverter
  vectors in the switching
• interval for two-level inverters but not for
  multilevel inverters
• The max phase may not determine the third cross,
  min phase
• may not determine the first cross
• Correct determination of the phases which
  determines the first
• -cross,second-cross and third-cross is required
  for multilevel inverters

200
Reference voltages and triangular carriers for a
five-level SPWM