EE466: VLSI Design

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EE466 VLSI Design

• 2009 Term Project

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Expectation

• To introduce you to basic research ideas
• Involves reading research paper
• Extraction of relevant parameters
• Simulation of circuits
• Presentation of results

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Low Swing Signaling

• Ideas
• Low Swing Signaling
• Reasons?
• Crosstalk
• Performance metrics
• Power dissipation metrics

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Low Swing Signaling

• Low Swing Interconnect Interface Circuits
• Hui Zhang Jan Rabaey
• 2 Circuits to compare

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Basic Idea

• Interface circuits

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Interfaces

• Conventional Level Converter (CLC)
• Reference
• Symmetric Source-Follower Driver with Level
  Converter (SSDLC)
• Level Converting Register (LCR)

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CLC

• VddL is the low swing reference voltage
• Uses static devices

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SSDLC

• Swing is limited between Vtn and Vdd-Vtn

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LCR

• REF voltage limits the swing

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Goals

• Simulate Circuits
• Consider a 3 wire bus
• Apply similar interface circuits on neighbors
• Study all crosstalk patterns
• Evaluate average delay on victim
• Evaluate worst case delay on victim
• Compute power and energy dissipation
• Present energy delay product metrics

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Milestones

• Reading Material
• Papers for reading on website
• Design of interface circuits
• Understand wire parameter extraction
• Reading material will be provided
• Technology and Reliability Constrained Copper
  Interconnects Part II Performance Implications
• Study crosstalk effects
• Present report with relevant metrics

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Deadlines

• Final submission
• Day of final exam