Digital Data Transmission Techniques

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Chapter 6 Digital Data Communication Techniques
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Asynchronous and Synchronous Transmission

• Timing problems require a mechanism to
  synchronize the transmitter and receiver
• timing (rate, duration, spacing) of the data bits
  must be the same at transmitter receiver
• receiver samples stream of data bits at bit
  intervals
• if clocks not aligned and drifting, the receiver
  will sample at wrong time after sufficient bits
  are sent
• Example for 1Mbps data stream, one bit will be
  transmitted every 1µs. With 1 clock drift at the
  receiver (faster or slower than transmitter),
  then wrong sampling will occur after 50 bit
  (500.01µs0.5 µs).
• Two solutions to synchronizing clocks
• asynchronous transmission
• synchronous transmission

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Asynchronous Transmission

• Avoid timing problem by not sending long stream
  of bits
• Data is transmitted one character at a time,
  where each character is five or eight bits in
  length
• Receiver can synchronize at the beginning of each
  new character
• idle state no transmission,
• NRZ-L signalling is common for asynchronous
  transmission
• The beginning of the character is signalled by a
  start bit
• This is followed by a character of 5 or 8 bits
  long
• The bits of the character are transmitted
  beginning with the least significant bit
• A parity bit is then added for the purpose of
  error detection
• The end of the character is a stop element.

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Asynchronous Transmission
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Effect of timing error in asynchronous
transmission

• Example The figure below shows the effects of a
  timing error of sufficient magnitude to cause
  error in reception. In this example, we assume a
  data rate of 10Kbps therefore each bit is 100µs
  duration. Assume that the receiver is fast by 6,
  or 6µs per bit time. Thus, the receiver samples
  the incoming character every 94µs. As we can see,
  the last sample is erroneous.

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Asynchronous Transmission- Behavior

• simple
• cheap
• overhead of 2 or 3 bits per char (20)
• good for data with large gaps (keyboard)

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Synchronous Transmission

• Block of data bits are transmitted as a frame
• Clocks must be synchronized
• can use separate clock line between transmitter
  receiver
• one side send one short pulse and the other side
  uses this pulse for clocking problem with long
  distances
• or embed the clocking information in the data
  signal
• Manchester encoding for digital signals
• carrier frequency for analog transmission
• Need to indicate start and end of block of data
• use preamble (8bit flag) and postamble (8bit
  flag)
• Control fields contain data link control protocol
  information
• More efficient (lower overhead) than asynchronous

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Synchronous Transmission

• More efficient (lower overhead) than asynchronous
  transmission (two start and stop bits for every 8
  bit character, (2/(28))10020).
• Example A frame in one of the standard schemes
  contains 48 bits of control, preamble, and
  postamble. Thus, for a 1000 character block of
  data, each frame consists of 48 bits of overhead
  and 100088000 bits of data, for a percentage
  overhead of only (48/(800048))1000.6.

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Types of Errors

• An error occurs when a bit is altered between
  transmission and reception (1 is transmitted and
  0 is received, and visa versa)
• Single bit errors
• only one bit altered
• caused by white noise
• Burst errors
• contiguous sequence of B bits in which first,
  last, and any number of intermediate bits in
  error
• caused by impulse noise or by fading in wireless
• effect greater at higher data rates
• Example An impulse noise event or fading event
  of 1µs occurs. At a data rate of 10Mbps, there is
  a resulting error burst of 10 bits. At a data
  rate of 100Mbps, there is an error burst of
  100bits.

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Error Detection

• Define the following probabilities
• Pb probability that a bit is received in error,
  known as Bit Error Rate (BER)
• P1 probability that a frame arrives with no bit
  error
• P2 probability that, with an error detecting
  algorithm in use, a frame arrives with one or
  more undetected errors
• P1(1-Pb)F where F is the number of bits per
  frame
• P21-P1

• Example a defined objective for the ISDN
  (Integrated Service Digital Network) is that the
  BER on a 64-Kbps channel should be less than
  10-6. Suppose that one frame with undetected bit
  error occur per day, and the frame length is
  1000bits. Determine P1 and P2.

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Error Detection

• Will have errors
• Detect using error-detecting code
• This code is added by the transmitter
• Recalculated and checked by the receiver
• Still chance of undetected errors
• Parity
• parity bit set so character has even (even
  parity) or odd (odd parity) number of ones
• even number of bit errors goes undetected

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Error Detection Process
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Parity Check

• Example If the transmitter is transmitting an
  IRA character G (1110001) and using an odd
  parity, it will append a 1 and transmit 11110001.
  The receiver examines the received character and,
  if the total number of 1s is odd, assumes that
  no error has occurred. If one bit (or any odd
  number of bits) is erroneously inverted during
  transmission (for example, 11100001), then the
  receiver will detect an error.

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Cyclic Redundancy Check (CRC)

• CRC is one of most common and powerful error
  detection code
• for block of k data bits, the transmitter
  generates an n-k bit sequence called Frame Check
  Sequence (FCS), such as the resulting frame
  length is n bits
• transmits the n bit frame which is exactly
  divisible by some number
• receiver divides frame by that number
• if no remainder, assume no error
• for math, see Stallings chapter 6

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Cyclic Redundancy Check (CRC)

• CRC can be clarified by three equivalent ways
• Modulo 2 Arithmetic
• Polynomials
• Digital Logic

• Modulo 2 Arithmetic binary addition with no
  carry (exclusive-OR (XOR) operation)

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CRC Modulo 2 Arithmetic
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CRC Polynomials

• A second way of viewing the CRC process is to
  express all values as polynomials in a dummy
  variable X, with binary coefficients
• The coefficients corresponds to the bits in the
  binary number

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CRC Polynomials
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Error Correction Process
FEC Forward Error Correction
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Error Correction Process

• On the transmission, each k-bit block of data is
  mapped into an n-bit block (n gt k) called a
  codeword, using an FEC (Forward Error Correction)
  encoder.
• At the receiver, the FEC decoder has four
  possible outcomes
• 1. If there are no bit errors, the decoder
  produces the original data block as output.
• 2. For certain error patterns, it is possible
  for the decoder to detect and correct those
  errors
• 3. For certain error patterns, the decoder can
  detect but not correct the errors, the decoder
  simply reports an uncorrectable error.
• 4. For certain, typically rare, error patterns,
  the decoder does not detect that any errors have
  occurred

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Block Code Principles

• The Hamming distance d(v1, v2) between two n-bit
  binary sequences v1 and v2 is the number of bits
  in which v1 and v2 disagree
• If v1011011 and v2110001, the d(v1, v2)3
• Consider the following assignment
• Suppose that a codeword block is received with
  the bit pattern 00100. This is a not valid code
  word, so an error is detected.
• The Hamming distance d(00000, 00100) 1
• d(00111, 00100) 2
• d(11001, 00100) 4
• d(11110, 00100) 3

• Most probably one bit in error (minimum
  distance) correct 00100 ? 00000

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Block Code Principles

• Consider the following assignment
• The Hamming distance between the code words
• d(00000, 00111) 3 d(00000, 11001) 3
  d(00000, 11110) 4
• d(00111, 11001) 4 d(00111, 11110) 3
  d(11001, 11110) 3
• ? The minimum hamming distance dmin3

• The maximum number of guaranteed correctable
  errors per code word is
• The number of errors that can be detected
  satisfies

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Block Code Principles

• With an (n , k) block code, there are 2k, valid
  code words and a total of 2n possible codewords
• The ratio of the redundant bits to data bits
  (n-k)/k is called the redundancy of the code
• The ratio of the data bits to the total bits k/n
  is called the code rate

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How Coding Improves System Performance

• For BER10-6, the coding gain 2.77dB

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Line Configuration - Topology

• Physical arrangement of stations on medium
• point to point - two stations
• such as between two routers / computers
• multi point - multiple stations
• traditionally mainframe computer and terminals
• now typically a local area network (LAN)

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Line Configuration Duplex

• Classify data exchange half or full duplex
• Half duplex (two-way alternate)
• only one station may transmit at a time
• requires one data path
• Full duplex (two-way simultaneous)
• simultaneous transmission and reception between
  two stations
• requires two data paths
• separate media or frequencies used for each
  direction

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