Design and Implementation of VLSI Systems

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Design and Implementation of VLSI
Systems (EN0160) Lecture 13 Power Dissipation
Prof. Sherief Reda Division of Engineering, Brown
University Spring 2007
sources Weste/Addison Wesley Rabaey/Pearson
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Power and Energy

• Power is drawn from a voltage source attached to
  the VDD pin(s) of a chip.
• Instantaneous Power
• Energy
• Average Power

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Dynamic power

• Dynamic power is required to charge and discharge
  load capacitances when transistors switch.
• One cycle involves a rising and falling output.
• On rising output, charge Q CVDD is required
• On falling output, charge is dumped to GND
• This repeats Tfsw times
• over an interval of T

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Dynamic power dissipation
load capacitance (gate diffusion
interconnects)
Energy delivered by the supply during input 1 ? 0
transition
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Capacitive dynamic power

• If the gate is switched on and off f0?1
  (switching factor) times per second, the power
  consumption is given by

• For entire circuit

where ai is activity factor 0..0.5 in
comparison to the clock frequency (which has
switching factor of 1)
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Short circuit current

• When transistors switch, both nMOS and pMOS
  networks may be momentarily ON at once
• Leads to a blip of short circuit current.
• lt 10 of dynamic power if rise/fall times are
  comparable for input and output

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Dynamic power breakup
Total dynamic Power
source Intel03
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Calculating dynamic power An example

• 200 Mtransistor chip (1.2 V 100 nm process Cg 2
  fF/mm)
• 20M logic transistors
• Average width 12 ?
• 180M memory transistors
• Average width 4 ?

• Static CMOS logic gates activity factor 0.1
• Memory arrays activity factor 0.05 (many
  banks!)
• Estimate dynamic power consumption per MHz.

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Static (leakage) power

• Static power is consumed even when chip is
  quiescent.
• Leakage draws power from nominally OFF devices

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Leakage example

• The process has two threshold voltages and two
  oxide thicknesses.
• Subthreshold leakage
• 20 nA/mm for low Vt
• 0.02 nA/mm for high Vt
• Gate leakage
• 3 nA/mm for thin oxide
• 0.002 nA/mm for thick oxide
• Memories use low-leakage transistors everywhere
• Gates use low-leakage transistors on 80 of logic

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Leakage power (continued)

• Estimate static power
• High leakage
• Low leakage

• If no low leakage devices, Pstatic 749 mW (!)

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Techniques for low-power design

• Reduce dynamic power
• a clock gating, sleep mode
• C small transistors (esp. on clock), short wires
  
• VDD lowest suitable voltage
• f lowest suitable frequency

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Dynamic power reduction via dynamic VDD scaling

• Scaling down supply voltage
• reduces dynamic power
• reduces saturation current
• ? increases delay ? reduce the frequency

Dynamic voltage scaling (DVS) Supply and voltage
of the circuit should dynamic adjust according to
the workload of our circuits and criticality of
the tasks
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Reducing static power

• Reduce static power
• Selectively use low Vt devices
• Leakage reduction
• - stacked devices, body bias, low temperature

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Leakage reduction via adjusting of Vth

• Leakage depends exponentially on Vth. How to
  control Vth?
• Remember Vth also controls your saturation
  current ? delay

• Sol2 dynamically adjust the bias of the body
• idle increase Vt (e.g. by applying ve body
  bias on NMOS)
• Active reduce Vt (e.g. by applying ve body
  bias on NMOS)

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Leakage reduction via Cooling

• Impact of temperature on leakage current

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Summary

• We are still in chapter 4
• We covered delay and power estimation
• Next time, we going to move into integrating the
  impact of wires into delay/power calculations