NMOS Field Effect Transistor

1
NMOS Field Effect Transistor

• MOSFET Metal Oxide Semiconductor Field Effect
  Transistor
• Four terminal device (gate, source, drain,
  substrate)
• Unipolar transistor one type of charge carrier
• FET is a current control mechanism based on an
  electric field established by the voltage applied
  to the control terminal

Gate (G)
Source (S)
Drain (D)
Metal
Oxide (SiO2)
Channel region
n
n
p-type substrate (Body)
Body (B)
2
NMOS Cross-section
S
Metal
G
Metal or Polysilicon
W
D
Oxide (SiO2)
n
Source Region
L
n
P-type substrate (body)
Channel Region
B
Drain Region
3
Creating a Channel for Current Flow

• A positive voltage is applied to the gate which
  forms an inversion layer, or an n-type channel

4
Operation with Small vDS
iD
5
Exercise 5.1

• Note that in the small signal linear range, iD is
  proportional to (vGS-Vt)vDS Find the constant of
  proportionality for the device below and the
  range of drain-to-source resistance for vGS2V to
  5V

Constant of proportionality
Drain-to-source resistance
6
Uniform Channel Approximation
Wwidth
VGgtgtVD and VS
VS
VD gt VS
x L
x 0
x
inversion channel
n
n
depletion region edge
y
p-type

• Assumptions
• Uniform behavior in the z (channel width)
  direction
• The mobility is a constant
• The x directed electric field is approximately a
  constant within the channel thickness (ych) at a
  given x. This is known as the gradual channel
  approximation.
• At a given x,
• The current is constant, independent the location
  of the chosen cross-section (i.e. independent of
  x)

Channel charge
Area
7
Charge per unit length in the channel (VGS gtgt VDS)
VGS
Gate Electrode (metal)
dx
Gate Oxide
v(x)
channel
drain
source
v(x) the voltage at point x
Charge dq
dv(x)the incremental voltage about point x
The voltage drop between the gate and the
channel, in excess of the threshold voltage
Vt determines the amount of charge
8
Derivation of the MOSFET current equation in the
Linear Region of Operation
é
ù
é
ù
y
W
r
ch
(
)
(
)
ò
ò

ê
ú
m
I
dz
qn
x
y
dy
E
x
ê
ú
,
n
n
x
ê
ú
ë
û
ë
û


w
y
0
0

W

(
)
x
Q
'
inversion
iDS
vGSVt 3V
vGSVt 2V
vGSVt 1V
vDS
Process Technology
Terminal potentials
200mV
Layout Geometries
9
Exercise 5.2

• Find the expression for rDSvDS/iD when vDS is
  small. Find the value of rDS for an NMOS
  transistor having kn20mA/V2,Vt1V, and
  W/L100mm/10mm when operated at vGS5V

10
Operation as vDS is Increased
11
Channel pinch off

• Increasing vDS causes the channel to acquire a
  tapered shape
• Eventually, as vDS reaches vGS-Vt, the channel is
  pinched off at the drain end
• Increasing vDS above vGS-Vt has little effect
  (theoretically no effect) on the channels shape

vDS ³ vGS-Vt
Source
Channel
Drain
vDS
vDS 0
12
Operation as vDS is Increased (cont.)
13
Higher Drain Voltages (pinch-off)
For Example VG3V Vt1V
VGDVG-VD1V just Vt
VGSVG-VS VGS3V
VS0
VDSVGS-Vt2V
VD gt VS
x L
x 0
x
inversion channel
n
n
y
p-type
depletion region edge
14
The Saturation Region of Operation
Square Law - i.e The current is proportional to
the voltage in excess of the threshold squared
15
MOSFET Transistor Operating Regions Summary
Linear (triode) Region
Pinchoff - onset of Saturation Region
Saturation Region
Figure taken from Semiconductor Devices, Physics
and Technology, S. M. Sze,1985, John Wiley Sons
16
MOSFET Operation Summary
Triode Region vGS gtVt, vDS lt vGS-Vt
Saturation Region vGS gtVt, vDS ³ vGS-Vt
17
PMOS Field Effect Transistors
18
Sub-threshold Region
MOS behavior
ID
Moderate inversion
Small current level lt 1mA
weak inversion
VGS sub-threshold
Bipolar-like behavior
junction leakage
3ft
VDS
In the sub-threshold regime
19
CMOS technology
Figure taken from supplemental material for
Digital Integrated Circuits, A Design
Perspective, Jan M. Rabaey,1996, Prentice Hall
20
MOSFET Circuit symbols
NMOS
PMOS
21
The iD-vDS Characteristics (NMOS)
iD

iG0
vDS

vGS
iSiD
-
-
Figure taken from supplemental material for
Digital Integrated Circuits, A Design
Perspective, Jan M. Rabaey,1996, Prentice Hall
22
iD vs. vGS Characteristic for an NMOS transistor
in saturation
iDS
vDS ³ vGS-Vt
vGS (V)
Vt
23
Large Signal Model of a MOSFET in Saturation
iG0
iD
G
D


vGS
vDS
-
-
vGS ³ Vt
S
vDS ³ vGS-Vt
24
Finite Output Resistance in Saturation
Source
Channel
Drain
vDSsat vGS-Vt

-

-
vDS-vDSsat
L
DL
25
Channel Length (Drain Current) Modulation due to
changes in VDS
saturation
triode
VA -(1/l)
26
Large Signal Model of the MOSFET Incorporating
the Output Resistance
27
Exercises

• 5.3 An enhancement mode transistor with Vt2V has
  its source terminal grounded and a 3V DC source
  connected to the gate. In which region of
  operation does the device operate for
• a) VD0.5V VDS 0.5V lt VGS-Vt, \ in triode
  region
• b) VD1V VDS 1V VGS-Vt, \ in saturation
  region (pinch-off)
• c) VD5V VDS 5V gt VGS-Vt, \ in saturation
  region
• 5.4 If the transistor above has kn20mA/V2,
  W100mm and L10mm, find the value of iD in the
  above cases - ignore the dependence of iD on vDS
  in saturation.

vD

3V
-
-
28
Exercises

• 5.6 An enhancement MOSFET with kn(W/L)0.2mA/V2,
  Vt1.5V, and l0.02V-1 is operated with vGS3.5V.
  Find iD at vDS2V and vDS10V. Determine rO at
  this value of vGS.

29
The iD-vDS Characteristics (PMOS)
V
-2V
GS
V
-3V
GS
iD
-1

iG0
vDS
V

-4V
GS
vGS
iSiD
-
-
Saturation
Triode
-2
V
-5V
GS
Figure taken from supplemental material for
Digital Integrated Circuits, A Design
Perspective, Jan M. Rabaey,1996, Prentice Hall
30
n-channel Enhancement Mode MOS Transistors

• Enhancement Mode Transistors. A normally open
  switch. At zero volts on the gate no current
  flows ( a positive Voltage must be applied to the
  gate to enhance a channel of electrons)

Drain
Drain
Gate
Source
Gate
Substrate
n
n
Source
p substrate
n-channel
Source - where electrons come from (-) Drain -
where electrons flow to ()
IDS
Channel is enhanced (resistive)
Channel is off
VGS
-VGS
0
31
n-channel Depletion Mode MOS Transistors

• Depletion Mode Transistors. A normally closed
  switch. At zero volts on the gate a current flows
  ( a negative Voltage must be applied to the gate
  to deplete the channel of electrons)

Drain
Drain
Gate
Source
Gate
Substrate
n
n
Source
n-channel
Source - where electrons come from (-) Drain -
where electrons flow to ()
p substrate
IDS
Channel is made stronger
Channel is depleted (Off)
VGS
-VGS
0
32
p-channel Enhancement Mode MOS Transistors

• Enhancement Mode Transistors. A normally open
  switch. At zero volts on the gate no current
  flows ( a negative Voltage must be applied to the
  gate to enhance a channel of holes)

Source
Drain
Gate
Source
Gate
Substrate
p
p
Drain
n substrate
p-channel
0
-VGS
VGS
Channel is enhanced
IDS
33
p-channel Depletion Mode MOS Transistors

• Depletion Mode Transistors. A normally closed
  switch. At zero volts on the gate a current flows
  ( a positive Voltage must be applied to the gate
  to deplete the channel of electrons)

Source
Drain
Gate
Source
Gate
Substrate
p
p
Drain
n substrate
p-channel
0
-VGS
VGS
Channel is depleted
IDS
34
The Body or Back Gating Effect on Threshold
Voltage
Source (S)
Gate (G)
Drain (D)
Vbody-Source Slightly (lt0.4V) Forward Biased
A slight body to source forward bias raises the
potential of the electrons in the substrate
reducing the gate voltage necessary to
invert the surface
n
Channel region
n
A reverse body to source bias lowers the
potential of the electrons in the substrate
increasing the gate voltage necessary to
invert the surface
p-type substrate (Body)
Gate (G)
Drain (D)
Source (S)
Channel region
n
n
Vbody-Source0
p-type substrate (Body)
Body (B)
Vt
Source (S)
Vt0
Gate (G)
Drain (D)
Vbody-Source Reverse Biased
n
Channel region
n
Gamma - Body Effect Parameter
p-type substrate (Body)
35
Example 5.1

• Design the circuit shown below so that the
  transistor operates at ID 0.4 mA and VD 1V.
  The NMOS transistor has Vt 2 V, mnCox 20
  uA/V2, L 10mm, and W 400 mm. Assume l 0.

36
Example 5.2

• Design the circuit shown below to obtain a
  current ID 0.4 mA. Find the value required for
  R and find the dc voltage VD. Let the NMOS
  transistor have Vt 2 V, mnCox 20 uA/V2, L
  10mm, and W 100 mm. Assume l 0.

Since VDG 0V, we are operating in the
saturation region.
Choose VGS 4V since 0V lt Vt and VD 4V.
37
Example 5.3

• Design the circuit shown below to establish a
  drain voltage of 0.1V. What is the effective
  resistance between drain and source at this
  operating point? Let Vt 1 V, and kn(W/L) 1
  mA/V2.

The MOSFET is operating in the triode region,
since the drain voltage is lower than the gate
voltage, and Vt is 1V.
Triode, if
38
Example 5.4 NMOS

• Analyze the following circuit to determine all
  the node voltages and branch currents, given that
  Vt1V and kn(W/L) is 1mA/V2. Neglect the channel
  length modulation effect (i.e. assume l0)

VDD 10 V

• Since the gate current is zero (why?), the
  voltage at the gate is simply determined by
  voltage division between RG1 And RG2, and since
  they are equal VG is VDD/2 or 5 Volts.
• Since the gate voltage is significantly higher
  than ground it is likely that the transistor is
  on, but we don not know if it is in the triode
  region of operation or in saturation.
• We will assume that it is saturated and solve the
  problem and then check the validity of our
  assumptions (often the hard part for beginners).
  The saturation equations are easier to work with
  and that makes a good choice for starting out. If
  our assumptions do not check out we have to go
  back and use the triode region equations

ID IS
RD 6 kW
RG1 10 MW
5 V
assumed
vS -
IS ID
RG2 10 MW
RS 6 kW

• The drain current has to be equal to the source
  current since IG is zero
• VGS 5 - 6,000(ID)
• And in saturation

39
Example 5.4 continued
VDD 10 V

• Again, in saturation
• Which is a quadratic Eq. in ID

RD 6 kW
RG1 10 MW
5 V
assumed
vS -
RG2 10 MW
RS 6 kW

• This yields two values for ID, 0.89 mA and 0.5 mA
• Which is valid for our assumption of saturation?
• For ID of 0.89 mA the source voltage would be
  6,000(0.00089) or 5.34 Volts which is higher than
  the gate voltage and since the gate to source
  voltage to turn the device on (i.e. threshold
  voltage) is 1 Volt the device would be off not
  saturated this answer is not valid.

• For ID of 0.5 mA the source voltage would be
  6,000(0.0005) or 3 Volts which means the gate to
  source voltage is 5-3 or 2 Volts which is greater
  than the threshold voltage (1 Volt) and the
  device is on. But is it saturated?
• The drain is at 10-(6,000)(0.0005) or 7 Volts
• VDS7-3 or 4 Volts
• Since VDS (4V) is greater than VGS-Vt (2V-1V) the
  device is by definition in saturation so our
  initial assumption was correct

40
Example 5.5 (PMOS)

• Design the following circuit so that the
  transistor operates in saturation with ID0.5mA
  and VD3V. Let the enhancement type PMOS
  transistor have Vt-1V and kp1mA/V2. Assume l
  0. What is the largest value that RD can have
  while still maintaining saturation-region
  operation?
• We were given the conditions to be met so lets
  start there, ID0.5mA
• VG to ground is VDD -VSG 5-(2)3V
• The gate voltage can be set by picking
  appropriate values of RG1 and RG2 in a voltage
  divider, for example, RG1 2MW and RG2 3MW
• The drain resistor value can be found from

VDD 5 V
RG1
assumed
vD 3 V -
RG2
RD
The border for saturation to linear occurs at
VDSVGS-Vt so VDSmax-2-(-1) -1V,
therefore VD to ground max is VDD-VSD5-(1)4V At
VD4V and ID0.5mA, RD8kW
41
Example 5.6 (depletion NMOS)

• The depletion MOSFET in the circuit is required
  to supply the variable resistor RD with a
  constant current of 100mA. If kn 20 mA/V2 and
  Vt -1 V, find the W/L ratio required. Also
  find the range that RD can have while the current
  through it remains constant at 100mA. Assume l
  0.
• The MOSFET in this circuit is conducting (VGS
  0). It must be operated in the saturation mode
  in order to conduct a constant current ID while
  RD (and VD) is varying.
• The saturated mode of operation will be
  maintained for

VDD 5 V
RD
vD -
assumed
Thus, RD can vary in range from 0 to 40 kW
42
Example 5.7 (depletion mode FETs)

• Design the circuit shown below to establish a dc
  voltage of 9.9V at the source. At this operating
  point, what is the effective resistance between
  the source and the drain of the transistor? Let
  Vt -1V and Kn(W/L) be 1 mA/V2.
• In this case the gate and the source are just
  slightly below the drain (0.1V) and VGS0. VDS is
  not greater than VGS-Vt (0.1 is not greater than
  0-(-1)) so the transistor is in the triode region
  and the current is
• We can now find RS by
• The effective source to drain resistance is

VDD 10 V
assumed
VS9.9V -
RS
43
Exercise 5.13

• Consider the circuit below where the voltage VD1
  is applied to the gate of another transistor, Q2.
  Assume that Q1 and Q2 are identical. Find the
  drain current and voltage of Q2. Assume l 0.
  (see example 5.3)

From example 5.3, VD4V and ID10.4mA. Q1 and Q2
are identical and have equal VGS. Assuming that
Q2 is also operating in the saturation mode, its
drain current will be identical to that of Q1,
0.4mA
Since VD2 gt VG2 (4V), we are indeed operating in
the saturation region.
44
MOSFET as an Amplifier
IDS-VDS Characteristic
saturation
DIGS Linear Output Change
DVGSgt Linear Input Change
DVDS does not change output much

• Since changes in the drain to source voltage does
  not change the output much we will focus on the
  IDS-VGS characteristic

45
MOSFET Amplifier Configuration

• We can obtain amplification of a small analog
  signal by use of an enhancement mode MOSFET.
• A dc voltage (bias) VGS, is applied along with
  the input signal to be amplified, vgs
  superimposed on it. The output voltage is taken
  at the drain and consists of a dc and ac
  response.
• A circuit for amplification is shown below
• This circuit is not practical because
• The dc voltage source at the input is difficult
  to implement
• Integrated circuit resistors take up too much
  room
• MOSFETs are used for loads

VDD

• To be used as an amplifier the MOSFET must be
  biased in the saturation region
• To find the dc bias we set the ac component of
  the input to zero and determine the dc drain
  current in saturation (we will neglect channel
  length modulation in this case, that is we will
  assume l0)

RD
iDS(t)
(DCac)
vDS(t) -
ac
vgs(t)
VGS
(DCac)
DC
46
The Signal Current at the Drain

• The dc voltage at the drain, VD will be equal to
  VDD - RDID
• To ensure saturation we must have
• Now we go back to the situation where we have
  both the dc bias and the ac signal
• The resulting total instantaneous drain current
  to be
• We can focus on the ac response if we keep the
  input signal small, such that

dc bias
non-linear ac response
ac response
47
Transconductance

• If the small-signal condition specified on the
  previous page is satisfied we can neglect the
  last non-linear term in the current equation and
  express iD as
• Where
• And we know that the ratio of id to vgs is the
  transconductance gm
• In general

48
Voltage Gain

• The total instantaneous drain voltage is
• Using the small signal condition
• The small-signal component of the drain voltage
  is
• The voltage gain is then given by

49
DC Bias with an ac small signal
iDS
tangent at Q

• The DC bias level determines the ac parameters
• By restricting the input signal swing to small
  values we can linearize the characteristic like
  we did for amplifier transfer characterisitcs

Bias Point - Q
IDS
t
ids (t)
VDD
VGS
RD
iDS(t)
0
0
vGS (V)
Vt
(DCac)
vDS(t) -
ac
vgs(t)
vgs (t)
VGS
(DCac)
input
DC
t
50
The Input and Output Signals
vGS

• When the gate to source signal is at its maximum
  the drain current is at its maximum. Maximum
  drain current means that the drop across the
  drain resistor is at its maximum or that the
  drain to source voltage of the MOSFET is at its
  minimum
• The output is therefore 180 degrees out of phase
  from the input. We have an inverting small signal
  amplifier in this configuration
• In order for the transistor to operate in the
  saturation region at all times there is a minimum
  drain voltage that must be maintained.
• The input signal must be small enough to keep the
  output above the minimum

vgs
vGS
VGS
t
vD
gmRD
VD
0
t
51
Small-Signal Saturation Equivalent Circuit Models

• From a small-signal point of view the FET behaves
  like a voltage controlled current source as shown
  on the top figure to the left.
• Th input resistance is high (ideally infinite)
• After the DC analysis is done to determine the ac
  parameters and then the ac equivalent circuit is
  drawn.
• A DC voltage source is ideally immune to changes
  in current so small ac voltage changes do not
  cause change in current (dI/dV is zero or R is
  zero) it is replaced by a SHORT circuit.
• Current source are replaced by OPEN circuits
• In the first model is was assumed that the drain
  current did not change with increasing VDS in
  saturation but we know that it does. The
  dependence can be modeled by a finite resistance
  ro, between source and drain, whose value is
  approximated by the equation shown at the left.

G
vgs -
gmvgs
D
S
D
G
vgs -
gmvgs
ro
S
52
Applying the small-signal model

• On the previous page VA 1/l . Which we can
  determine from the Id-Vd characteristic,
  typically in the 10kW to 1,000kW range
• Remember, the ac parameters, gm and ro depend on
  the DC bias point
• The gain for the following circuit is given below
  (note that ro reduces the gain)

VDD
ac small-signal circuit
RD
iDS(t)
D
G
(DCac)
vgs(t) -
vDS(t) -
gmvgs
ro
vds -
ac
vgs
RD
vgs(t)
VGS
DC
(DCac)
53
The Transconductance - gm

• The transconductance of a bipolar transistor is
  proportional to the bias current (not the square
  root of it) and does not depend on the physical
  size or geometry
• We can write gm in another useful way, as shown
• Vt is 25mV but
• MOSFETs are smaller and use less power

• The transconductance as we have seen already is
  the incremental change in drain current due to an
  incremental change in gate voltage or
• If we solve the saturation current equation for
  VGS-Vt we get
• and by substitution
• So gm is proportional to the square root of the
  dc bias current
• At any bias current gm is proportional to the
  square root of W/L

54
Example 5.8 - Complete Amplifier Analysis

• In the following circuit, a discrete MOSFET
  amplifier is shown in which the input signal vi
  is coupled to the gate via a large capacitor, and
  the output signal at the drain is coupled to the
  load resistance RL via another large capacitor.
  We will assume that the coupling capacitors are
  large enough so that they act as short circuits
  for the ac signal frequencies of interest. We
  wish to analyze the amplifier circuit to
  determine its small-signal voltage gain and its
  input resistance. The transistor has Vt1.5V,
  kn(W/L) 0.25mA/V2, and VA 50V.

VDD15V

• Start by doing the dc analysis

RD10kW
RG10MW
vDS(t) -
vi -
ac
RL10kW
Rin
The other solution is not valid (contradictory)
55
ac equivalent circuit for Example 5.8
VDD15V
RD10kW
RG10MW
VDD is shorted to ground in the ac circuit
vDS(t) -
vi -
ac
RL10kW
Rin
ac small-signal equivalent circuit
RG
D
G
vgs -
vgs -
vo -
gmvgs
ro
vi
RD
RL
Rin
56
ac analysis for Example 5.8

• The value of gm is given by
• The MOSFET output resistance ro is
• We can now us the ac equivalent circuit to
  determine the expression for the output voltage
  in terms of the gate to source small-signal
  voltage

• The value of the voltage gain Av is given by

Since RG is so large
57
Evaluation of the Input Resistance for Example 5.8

• To find the input resistance we note that the
  input current is given by

58
The Source Absorption Theorem (Appendix E)Used
to derive the T Model for a MOSFET
Node 2
Node 1
Node 2
Node 1
59
The T Equivalent Circuit Model
ig 0
id
X
G
G
vgs -
vgs -
gmvgs
gmvgs
gmvgs
D
D
is
S
S
D
ig 0
id
X
id
G
vgs -
ig 0
gmvgs
gmvgs
G
gmvgs
vgs -
D
is
S
S
is
60
Modeling the Body Effect

• The body effect (or back gate effect) occurs when
  the source is NOT at the same potential as the
  substrate (body). The substrate acts as a second
  gate and therefore we include a second dependent
  current source in our model, as shown below

the dependence is linked to the threshold voltage
D
G
vgs -
gmvgs
gmbvbs
ro
B

vbs
S
61
Exercise 5.17

• For the following amplifier, let VDD 5V, RD
  10kW, Vt 1 V, kn 20 mA/V2, W/L 20, VGS
  2V and l 0.
• Find the dc current ID and the dc voltage VD
• Find gm
• find the voltage gain
• If vgs 0.2sinwt volts, find vd assuming that
  the small-signal approximation holds. What are
  the maximum and minimum values of vD.
• Use the following equation to find the various
  components of the drain current

VDD
RD
iDS(t)
(DCac)
vDS(t) -
ac
vgs(t)
VGS
(DCac)
DC
62
Exercise 5.17 continued

• Using the following identity show that there is a
  slight shift in ID (by how much?) and that there
  is a second harmonic component (2nd harmonic has
  a frequency of 2w)
• Express the amplitude of the second harmonic
  component as a percentage of the amplitude of the
  fundamental (this is known as the second-harmonic
  distortion)

63
Biasing MOSFET Amplifier Circuits

• Biasing is the establishment of an appropriate dc
  operating point for the transistor.
• An appropriate dc bias point has a stable and
  predictable dc drain current ID, and a dc drain
  to source voltage that ensures operation in the
  saturation mode for all expected input signal
  levels.
• Discrete component MOSFET circuits are not common
  but we will use them to introduce various biasing
  techniques.

IDS-VDS Characteristic
saturation
DIGS Linear Output Change
DVGSgt Linear Input Change
DVDS does not change output much
64
MOSFET Biasing - Single Supply

• Plus side of MOSFET bias circuit design - the
  gate current is zero (easier to design)
• Negative side of MOSFET bias circuit design - Vt
  (VGS response) varies more than vBE does in BJT
  circuits.
• The circuit shown at the right is commonly used
  when a single power supply is available. A
  voltage divider is used to establish a fixed dc
  voltage at the gate.
• Since the gate current is zero the two gate bias
  resistors RG1 and RG2 can be selected to be very
  large (MW range)
• This will provide a large amplifier input
  resistance
• A resistor, called a self bias resistor is
  connected to the source. If the device is turned
  on more (more source current) the drop across
  source resistor will increase and reduce the
  current. A balance (negative feedback) situation
  will be created.
• RD is selected to be as high as possible to
  obtain high gain but small enough to allow for a
  large enough output signal swing at the drain
  while still keeping the MOSFET in saturation at
  all times.

65
MOSFET Biasing - Dual Supplies

• For symmetric supplies (positive and negative of
  the same magnitude) a simpler bias arrangement
  can be used.
• The resistor RG establishes a dc ground at the
  gate of the transistor.
• Directly grounding the gate will also establish a
  dc bias but RG is used to increase the input
  resistance seen by a signal source that may be
  capacitively coupled to the gate
• RD is selected to be as high as possible to
  obtain high gain but small enough to allow for a
  large enough output signal swing at the drain
  while still keeping the MOSFET in saturation at
  all times.

66
MOSFET Biasing with a Constant Current Source

• Having a constant current source establishes the
  source and drain current level.
• We will look at how to construct a constant
  current source shortly
• As before RD is selected to be as high as
  possible to obtain high gain but small enough to
  allow for a large enough output signal swing at
  the drain while still keeping the MOSFET in
  saturation at all times.
• As before, The resistor RG establishes a dc
  ground at the gate of the transistor.
• Directly grounding the gate will also establish a
  dc bias but RG is used to increase the input
  resistance seen by a signal source that may be
  capacitively coupled to the gate

67
Common-Source Circuit with Resistive Gate Feedback

• The feedback resistor RG forces the dc voltage at
  the gate to be the same as that of the drain
  (since IG 0).
• The input can be capacitively coupled to the gate
  and the output can be taken at the drain to form
  a simple common-source amplifier.
• The output signal swing is limited on the low
  side since the drain (which is tied to the gate)
  must be high enough to satisfy the threshold
  voltage gate to source. If the output goes too
  low the transistor slips out of saturation into
  the triode region of operation and the output
  will be distorted.
• As before RD is selected to be as high as
  possible to obtain high gain but small enough to
  allow for a large enough output signal swing at
  the drain while still keeping the MOSFET in
  saturation at all times.

68
Biasing of Discrete MOSFET Amplifiers

• Four circuits for biasing the MOSFET in
  discrete-circuit design.

common-source circuit
constant current source
classical arrangement
2 power supplies
69
Biasing of Discrete MOSFET Amplifiers

• Exercise 5.22 Design the circuit below for a
  MOSFET having kn(W/L) 0.5 mA/V2 and Vt 2V,
  and utilizing two power supplies, 10V. Design
  for ID 1mA and allow for a signal swing at the
  drain of 2V. The amplifier is required to
  present a 1MW input resistance to a signal source
  that is capacitively coupled to the gate. Assume
  l0.

Where we have neglected the signal component of
VG
To allow for a 2V signal swing at the drain,
70
Design Philosophy

• The circuits that we have just looked at are not
  suitable for integrated circuit design.
• They use too many resistors which take up room
  and are therefore expensive.
• It turns out that since we are making small
  MOSFETs anyways, that if we can use transistors
  that act sort of like resistors we can make much
  smaller (more dense) circuits.
• The coupling capacitors also take up way to much
  room so coupling and bypass capacitors are not
  used in the design of MOSFET amplifier circuits.
• You can learn more about integrated circuit
  fabrication in EGRE435 during the fall of 2000.
• You can learn more about MOS analog circuit
  design in EGRE307 during the fall of 2000.
• You can learn more about MOS digital circuit
  design in VLSI Design EGRE429.

71
Basic MOSFET Constant Current Source

• Use a reference current through one transistor
  (Generated through Q1) to set the voltage across
  the gate to source of another transistor (Q2) and
  hence replicate the reference current through the
  drain of the second transistor.
• Q1 is saturated since VGS VDS

For Q1,
For Q2,
constant current source
current mirror
72
Effect of VO on IO

• In the previous current source description we
  assumed that the transistor Q2 is operting in
  saturation

Region of constant current operation
73
Example 5.9

• Given VDD5V and using IREF100mA, it is required
  to design the circuit shown below to obtain an
  output current whose nominal value is 100mA.
  Find R if Q1 and Q2 are matched, have channel
  lengths of 10mm and channel widths of 100mm,
  Vt1V and kn20mA/V2. What is the lowest
  possible value of VO? Assuming the fabrication
  technology results in an Early voltage that can
  be expressed as VA10L, where L is in microns and
  VA in volts, find the output resistance of the
  current source. Also find the change in output
  current resulting from a 3V change in VO.

Since L10mm,
The output current will be 100mA at VOVGS2V.
If VO changes by 3V, the corresponding change in
IO will be 3,
74
Current-Steering Circuits
threshold voltage for n-channel devices
threshold voltage for p-channel devices
75
Basic Configurations of Single-Stage IC MOS
Amplifiers
76
Resistive Load Common Source Amplifier

• An ideal current source has an infinite
  resistance, the current does not depend on the
  voltage at the node to which it is connected, but
  what happens if we use a resistive load

• The resistor constrains the current flow through
  the transistor and vice-versa. For the solid
  resistor load curve plotted on the transistor
  characteristic shown below the resistance is less
  than that of the dashed curve.
• On the solid curve the valid operating points
  (curve intersections) are labeled with a letter
  and on the dashed curve the letters have a prime
• On the next page we plot the voltage transfer
  characteristic of this amplifier

Load curve
Q1 in triode
Q1 in saturation
VR -
D
C
B
D
Vin
G
A
D
S
A
1
2
3
4
5V
0
common-source
Vout
VRVDD-VDS
77
Resistive Load Common Source Amplifier continued

• The plot of the transfer characteristic of the
  common-source amplifier with a resistive load is
  shown below
• Since the resistor is not an ideal current source
  the gain varies with the load resistance
• The higher the load resistance the higher the
  gain but the smaller the allowed input signal
  swing (an still have the transistor saturated)

5 4 3 2 1 0
saturation
A
R1gtR2
gain is proportional to the slope Gain1gtGain2
Vout
B
A
C
D
triode
B
D
C
0 1 2 3 4
5
Vin
78
The CMOS Common-Source Amplifier(PMOS current
source load)

• If the PMOS active load device is made with a
  long channel then lambda is small (the magnitude
  of VA is large or the transistor output
  resistance ro is large). In other words a long
  channel load acts more like an ideal current
  source.

Q2 in triode
Q2 in saturation
one curve not a family of curves
0
i-v characteristic of the active-load Q2
CMOS common-source amplifier circuit
79
Graphical construction to determine transfer
characteristic

• We expect to have a transfer characteristic that
  has a high gain since output resistance of the
  load transistor can be made high (long channel)
• The load curve is like a high value resistor that
  has been translated upwards
• We are most interested in the area of
  intersection between A and B for amplification

80
Transfer Characteristic of the active load
common source amplifier

• When the input is low the load transistor is in
  the triode region, as the input voltage is
  increased the active load becomes saturated.
• The gain is relatively high and depends on the
  output resistance of the transistor used in the
  current mirror

81
Small-signal equivalent circuit of the
common-source config.
D1,D2
S1,S2
Since ro1 and ro2 are usually large the gain can
be large without taking up a lot of room on the
chip with an integrated resistor.
If we use physically based parameters for the
transistors we get a design equation in terms of
the transistors length, width, transconductance,
output resistance and reference current source
value Voltage gains on the order of 20-100 are
obtained using CMOS common-source
configuration The source of each device is
connected to the body so the body effect on the
threshold voltage is not a factor
82
Effect of RS on AC gain

• In section 5.6 we discussed various DC biasing
  schemes and in those schemes we saw that the
  source resistor, RS (like its counterpart RE in
  the BJT case) provides negative feedback to the
  gate to source voltage and helps to stabilize the
  DC value of ID.
• If the DC bias point of the gate is increased the
  source current will increase but not by as much
  as when there is no source resistance
• This source resistance DOES affect the AC gain!
• Consider the case of a MOSFET biased to have a gm
  of 30mA/V, rO16KW, and RD470W
• AC model WITHOUT RS

D
G
vgs(t) -
gmvgs
vo -
ro
vi
RD
83
Effect of RS on AC gain (cont.)

• Now consider AC gain WITH RS, let RS10W

• More easily analyzed with the T model

D
D
G
vgs(t) -
vo -
gmvgs
vo -
ro
vi
RD
G
gmvgs
vgs -
vi
S
84
The use of a Source By-Pass Capacitor

• In the circuit shown on this page, at low
  frequencies, the source capacitor CS is an open
  circuit and the source resistance has a voltage
  drop across it which reduces the gate to source
  voltage across the transistor.
• On the next page the ac equivalent circuit is
  shown

VRD -
D
G
S
common-source with a source resistance
85
The use of a Source By-Pass Capacitor (ac circuit)
S1
CS short circuit (high frequencies)
CS open circuit (low frequencies) Note that Vgs
does not equal vi now
86
The CMOS Common-Gate Amplifier

• In this case a constant dc level is applied to
  the gate of the transistor and the input signal
  is applied to the source
• The signal source at the gate will be zero (hence
  the name common gate)
• There will be a potential difference between the
  source and the bulk (body) so we need to use the
  model which includes that effect.

G1
D1,D2
-
S1
B1
Body effect
common-gate amplifier viVSG voVDG
Vgs1-vi vbs1-vi
small-signal equivalent circuit
87
Simplified circuit
D1,D2
S1
Input resistance (input node equation)
output node equation
if 1/ro1ltltgm1

• The body effect adds to the gain but reduces the
  input resistance
• The active load (ro2) reduces the gain but
  slightly increases the input resistance
• By comparison the Common-Gate configuration has a
  gain similar to that of the common-source
  amplifier but the input resistance is much lower
• The common-gate configuration is used in a
  combination circuit called a cascode amplifier
  that we will study later in EGRE307.

88
The Common-Drain or Source-Follower Configuration

• The common-drain or source follower configuration
  is used as buffer amplifier. Although its voltage
  gain is less than unity it has a low output
  resistance and is therefore capable of driving
  low impedance loads with little loss of gain.
• Typically found in the output stage of a
  multi-stage amplifier.
• The fact that its impedance is buffered can be
  used to extend the high-frequency response range
  of amplifiers and speed up digital circuits.
• Vdd is at signal ground hence the name common
  drain
• The input impedance is very high since it is the
  gate of a MOSFET (THIS IS A VERY BIG ADVANTAGE
  OVER BJTs)

Signal Ground
common-drain or source-follower
small-signal equivalent circuit (again the body
effect is included)
Use the source absorption theorem to transform
the dependent source into a resistance 1/gmb1
89
Simplified circuit
G1
S1
0
The body effect reduces the gain by 10 to 30
percent
typically 0.1ltclt0.3
90
NMOS Load Devices - Saturated Enhancement Mode
Saturated Enhancement Mode Load VGSVDS therefore
always saturated
VDS2 -
locus of points on many curves
D2
VGSVDS
G2
D
S2
VDS1Vout -
D1
G1
G
VGS1Vin
S
S1
0
VGS2VDS2
x
x
x
0
91
NMOS Amplifier with Enhancement Load
Load curve
B
A
0
I Q1 cutoff
A
II Q1 in saturation
III Q1 in triode region
B
Due to the body effect on Vt VSB for Q2 is not
equal to zero (reduces the gain)
0
92
NMOS Amplifier with Enhancement Load
Positives Uses the same type of device for the
load as the driver (enhancement) Negatives Lower
Gain than the Depletion Mode Load Smaller output
signal swing (The output does not go all the way
up to VDD)
93
NMOS Load Devices - Saturated Depletion Mode
DepletionMode Load, VGS0 Always on
Depletion Mode Load VGS0 Always on
In saturation
IDS
D
G
S
VGS
triode
saturation
0
94
NMOS Amplifier with Depletion Load
95
NMOS Amplifier with Depletion Load
I
II
III
IV
Load curve
A
C
B
B
A
0
C
Positives Higher Gain than the Saturated
Enhancement Mode Load Larger output signal swing
(all the way up to VDD) Negatives Requires a
different type of device (depletion) for the
load and is therefore more complicated
Q1 Saturation Q2 Saturation
Q1 Off Q2 Triode
III
I
Q1 Saturation Q2 Triode
Q1 Triode Q2 Saturation
II
IV
96
The CMOS Digital Logic Inverter

• For any IC technology used in digital circuit
  design, the basic circuit element is the logic
  inverter.
• The inverter uses two matched enhancement-type
  MOSFETS an n-channel and a p-channel. The body
  of each device is connected to its source which
  eliminates any body effect.

simplified inverter circuit
CMOS inverter
97
Circuit Operation

• We assume that the n-channel device is the
  driver, and the p-channel device is the load.
• When the input is high, vOVOL0 Volts, and the
  power dissipation in the inverter is 0.

Operation of the CMOS inverter when vI is high
98
Circuit Operation, contd

• We assume that the n-channel device is the
  driver, and the p-channel device is the load.
• When the input is low, vOVDD, and the power
  dissipation in the inverter is 0.

Load curve
Operating point
0
Operation of the CMOS inverter when vI is low
99
Circuit Operation, contd

• The basic CMOS logic inverter behaves as an ideal
  inverter
• The output voltage levels are 0 and VDD, and the
  signal swing is the maximum possible. This
  results in wide noise margins.
• The static power dissipation in the inverter is 0
  
• A low-resistance path exists between the output
  terminal and ground (in the low-output state) or
  VDD (in the high-output state). The low output
  resistance makes the inverter less sensitive to
  the effects of noise and other disturbances.
• The active pull-up and pull-down devices provide
  the inverter with high output-driving capability
  in both directions.
• The input resistance of the inverter is infinite
  (because IG0). Thus the inverter can drive an
  arbitrarily large number of similar inverters
  with no loss in signal level.

100
Voltage Transfer CharacteristicPMOS Load Lines
Figure taken from supplemental material for
Digital Integrated Circuits, A Design
Perspective, Jan M. Rabaey,1996, Prentice Hall
101
CMOS Inverter Load Characteristics
Figure taken from supplemental material for
Digital Integrated Circuits, A Design
Perspective, Jan M. Rabaey,1996, Prentice Hall
102
The Voltage Transfer Characteristic
For QN,
For QP,
103
The Voltage Transfer Characteristic, contd
QN in saturation QP in triode
Slope -1
QN off
A
B
QN in saturation QP in saturation
Slope -1
C
QP in saturation QN in triode
QP off
D
104
The Complementary MOS (CMOS) Inverter

• Complementary means both nMOS and pMOS
  transistors are used
• A polite tug OWar! Only one device pulls at a
  time
• A High Voltage on Vin turns On the NMOS device
  and turns Off the PMOS device
• A Low Voltage on Vin turns off the NMOS and turns
  On the PMOS
• Power is dissipated only when the output is
  switching from low to high or high to low

5 V
5 V
Vgsp Vgp-Vsp 5-5 0
s5
g5
source of holes
open
gate
p channel (n well)
drain for holes
Vin 5V
Vout 0 V
Vin
Vout
drain for electrons
closed
n channel (p wafer)
g5
gate
s0
source of electrons
Vgsn Vgn-Vsn 5-0 5
5 V
The source is where charge carriers come from and
the drain is where they flow to, holes come from
the higher voltage and flow towards a more
negative terminal, electrons come from the more
negative terminal and flow towards the positive
s5
Vgsp Vgp-Vsp 0-5 -5
g0
closed
Vin 0
Vout 5V
Vgsn Vgn-Vsn 0-0 0
open
g0
s0
105
How are Noise Margins Determined?
slope 1

• The slope of the voltage transfer characteristic
  of an inverter is the gain.
• There are three key points on the gain plot
• The point at which the magnitude of the gain is
  first equal to unity (45 degrees)
• The point at which the magnitude is maximum
• The point second point at which the gain is again
  equal to unity

5
VOH
4
slope Maximum 5
VOUT (Volts)
3
2
slope 1
1
VOL
VIN (Volts)
0
2
4
5
1
3
VIH
VIL
gain slope
max
5
1
VIN (Volts)
106
What Noise Margins really mean

• On the previous page VIL was equal to 1.2V and
  VIH was equal to 3V
• VOL was equal to 0.7V and VOH was equal to 4.9V
• The Noise Margins are defined as follows
• NML VIL - VOL in our case
  1.2 - 0.7 0.5 Volts
• NMH VOL - VIL
  4.9 - 3.0 1.9 Volts

slope 1
VOH
5
slope Maximum 5
4
VOUT (Volts)
3
2
slope 1
VOL
1
VIN (Volts)
0
2
4
5
1
3
VIL
VIH
What the output produces
What the input accepts
solid high
5V
High VOH (5- 4.9) V
Marginal High NMH (5-3)-(5-4.9) 1.9V
VIH 3V and up
solid signals
Marginal Low NML 1.2-9.70.5V
VIL 1.2V
Low VOL (0.7- 0) V
solid low
0V
107
How does an Inverter (with gain) restorea poor
signal level?

• Assume that we have two identical inverters in
  series and that they both have the same voltage
  transfer characteristic given below.
• Lets say that the input to the first inverter is
  3.1 Volts, which is about as marginal a high
  signal as will be recognized as a high by the
  inverter.

5

• The output of the first inverter will be _____??
  If we take that as the input to the second
  inverter the output of the second inverter will
  be ___ ?? Volts.
• Is it a solid high?
• The inverter supplies (5 and ground) and the
  gain drives unknown and marginal signals towards
  solid levels

VOH
??
3.1
4
VOUT (Volts)
3
2
slope 1
1
VOL
0
VIN (Volts)
4
2
3
5
1
Input to inverter 1 3.1V
VIH
VIL
108
Solution to previous page
5
VOH
0.65
5
3.1
4
VOUT (Volts)
3
2
slope 1
1
VOL
0
VIN (Volts)
Output of inverter 1 0.65V
2
4
5
1
3
Input to inverter 1 3.1V
VIH
VIL
Input to INV 2
109
Propagation Delay and Rise and Fall Times of a
signal
vI
VOH
90 of (VOH-VOL)
Input Signal
50 1/2(VOLVOH)
10 of (VOH-VOL)
VOL
tr
tf
Time
tPHL
tPLH
vO
VOH
Output Signal
VOL
tTLH
tTHL
Time
110
The Analog Switch

• The MOSFET is often used as a voltage-controlled
  switch.
• The voltage applied to the gate of each QN and QP
  turns them on and off.
• In the off position, the MOSFET behaves as an
  open circuit between drain and source
• In the on position, the MOSFET presents a
  resistance rDS between drain and source

for small vDS

• More stringent requirements are placed on an
  analog switch, relative to a digital switch.
• When the switch is open, we want it to operate as
  an open circuit--the off-resistance switch should
  be very high (ideally infinite)
• A high on-resistance would result in signal
  attenuation
• The switch should be bidirectional (able to
  conduct in both directions)

Analog Switch
111
Circuit Operation

• Notice that terminals are not labeled they are
  interchangeable because the MOSFET is a
  symmetrical device.
• In general, the drain is the terminal which is at
  the higher voltage.

vC high vA positive
vC high vA negative
112
Equivalent Circuits for Transmission Gate
113
CMOS Transmission Gate and Circuit Symbol

• Compared to the single NMOS switch, the
  transmission gate provides better performance at
  the expense of greater circuit complexity and
  chip area.

114
MOSFET Internal Capacitances and High-Frequency
Model

• The MOSFET has internal capacitances, however,
  they are neglected in the small-signal model.
• The gain of every MOSFET amplifier falls off at
  some high frequency.
• The MOSFET model must be augmented by including
  internal capacitances.
• There are basically two types of internal
  capacitances in the MOSFET
• The gate capacitive effect the gate electrode
  (polysilicon) forms a parallel-plate capacitor
  with the channel, with the oxide layer serving as
  the capacitor dielectric.
• The source-body and drain-body depletion-layer
  capacitances these are the capacitances of the
  reversed-biased pn junctions formed by the n
  source region (source diffusion) and the p-type
  substrate, and by the n drain region (drain
  diffusion) and the substrate.
• There will be five capacitances in total
• Cgs, Cgd, Cgb, Csb, and Cdb, where the substrates
  indicate the location of the capacitances in the
  model.

115
The Gate Capacitive Effect

• The gate capacitive effect can be modeled by
  three capacitances Cgs, Cgd, and Cgb.
• In the triode region at small vDS
• In saturation
• In the cutoff region
• Overlap capacitance

May be zero depending on the bulk potential
116
The Junction Capacitances
For source diffusion, the source-body
capacitance, Csb
Csb0 is the value of Csb at zero body bias VSB is
the magnitude of the reverse-bias voltage V0 is
the junction built-in voltage
For drain diffusion, the drain-body capacitance,
Cdb
Cdb0 is the capacitance value at zero
reverse-bias voltage VDB is the magnitude of the
reverse-bias voltage V0 is the junction built-in
voltage
The above formulas assume small-signal operation.
117
The High-Frequency MOSFET Model
118
Unity-Gain Frequency (fT)

• The unity-gain frequency (fT) is defined as the
  frequency at which the short-circuit current-gain
  of the common-source configuration becomes unity.

The magnitude of the current gain becomes unity
at the frequency