Herv Lebbolo, Franois Rossel , Aurore SavoyNavarro

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Electronics of the Silicon Envelope

• Hervé Lebbolo, François Rossel , Aurore
  Savoy-Navarro
• LPNHE-Universités de Paris 67/IN2P3CNRS
• TOPICS
• Main parameters of the Si-Envelope
• Front-End Issues
• Long shaping time
• Proposed F.E schema
• Digitization on detector F.E
• DAQ Trigger very preliminary ideas

DAQ session, ECFA-DESY Extended Studies
Amsterdam, 1st to 4th April 2003
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The Si-Envelope componentsdue to their location
the functions of each piece of the Si-envelope
may (slightly) differ
Si-FCH
SET
SIT
FTD
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As in AMS Si-tracker, we propose to build long
ladders made of N sensors bonded to each other
F.E. electronics
connector
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The Si-envelope components in a few numbers
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The Front-End Electronics issues

• Starting point the AMS electronics R.O. System
• Proposed Front-End design the basics
• The Long shaping time
• Power consumption main goal passive cooling
• Tracking any possible way to spare power
• dissipation in the electronics on-detector
• gt Look for power cycling of electronics
• Digitization on the detector F.E. ?

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Starting point the AMS Si-tracker Readout system
(With particular thanks to G. Ambrosi, Ph.
Azzarello, W.Lusterman and the ETH-Zurich,
Geneva U. Peruggia U. AMS teams for their
support)
Tracker Front-End
Tracker Data Reduction
12 bit low power A/D (CLC949), as need large
dynamic range /- 100 MIPs dig. _at_ 5
MHz A/D coupled to DSP via FPGA (Xilinx
XC4013) buffer for up to 3 evts sequencer for
FE timing signals and synchro data
transfer. 16 bits-DSP _at_30MHz for calib and data
compression
Input Capa 33 72 pF VA_hdr/AMS64 64
charge ampli CR-RC shaper SH 64 ch
connected to voltage-current output buffer by
analog mux? seq. RO_at_ up 10 MHz Measured
ENC (3504/pFxC) electrons at 6 µsec peaking
time For ladder of 116 or 232 cm, input C 1.4 pF
x 116 or 232 ? N350 4xC.
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AMS2 new improved Readout system
By courtesy of G. Ambrosini
New Front End New hybrid VA_hdr9a,
0.8µ Internally generated biases, internal calib
capa Nominal gain 1.4 µA/fC Nominal peaking time
6 µsec ENC(300 Cdet x 5/pF)e- ? Good gain
stability small pedestal spread

• New readout scheme
• Simplified and HCC
• (Hybrid Control Circuit)
• Minimize digital cable line
• Control daisy chain of VA
• Increase system reliability
• Follows space rules

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Long ladder prototype
Lab test bench _at_LPNHE-Paris
A long ladder made of 7 AMS sensors has been
built at Geneva U. (assembling mounting),
bonded at CERN (ETHZ), allowing a variable length
for test L N1, 2, 4, 8 x 28 cm
long This long ladder is ready by 2nd of
April equipped with AMS FE electronics
(VA Preampli) or direct access at the µcrostrip
output. First complete
test on lab test bench at Geneva U. will be
extensively pursued in Paris Also starting
simulation studies on new FERO possible
designs (Ongoing similar studies at UC Santa
Cruz, on a 2 m long ladder)
Sensors 70.0x40.1 mm2 300 µm depth 110µm/208µm
RO pitch p(junction side) n(ohmic side)
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The prototypedlong ladder
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Protyped ladder VFE electronics
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Proposed F.E. Readout chain very preliminary
ideas
512 channels/ladder
2560 channels/drawer
A/D0.35µtechno, 8 bits 1MHz clock, 1.2mW
Main concern low noise and sparing power
dissipation at each corner of on-detector
electronics
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Cooling studies
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What infos do we need from the Si-tracker?
1) Detector occupancy? Will be different
according to the detector location
SET preliminary studies ? occupancy ? 1
SIT, FTD or Si-FCH should have higher
occupancies (higher
backgrounds) ? SPARSIFICATION on
detector F.E. ? 2) Double Multiple hit rates ?
Thus ambiguities must be estimated 3) Pulseheight
info (Q) needed? Yes if cluster centroid
(? 8 bit A/D ?) 4) Timing information ? R.O both
ends of the long ladder? 5) Pedestal substraction
on board? 6) DSP-like processing for eventual
cluster algorithm and eventual fastrack
processing algorithm at what level in the
electronic chain ??? 7) Power dissipation
studies preliminary results ? dont seem to be a
major issue (more
detailed ongoing studies) All these issues must
be studied with electronics and physics /or
detector performance simulations and tests on the
test bench (just starting . . .)
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Output of the signals very preliminary proposal
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DAQ intermediate trigger very preliminary
ideas
Based on the current experience with the trigger
system related to the tracking system in CDF, we
are foreseeing to study a Fastrack
trigger (or realtime processing) system that
could be used to 1) Do a fast clustering
and determine in realtime the cluster centroid
2) Do a fast tracking for stiff tracks (above 1
or 1.5 GeV/c momentum) with the overall
Si tracking information, i.e. starting
with the SIT SET and then linking to the
µvertex informations And
similarly in the forward region, perform a track
segment reconstruction in FTD and Si-FCH,
separately and possibly link them.
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Concluding remarks
Our main efforts are currently focusing on
developing the Lab test bench and starting an
extensive detailed study of the long ladder
prototype with variable length and different
possible Front-Ends The starting scheme AMS FE
and RO system Also looking for compatibility with
the general RO DAQ frame of the LC experiment
In parallel , both electronics and physics
detector performances simulation studies are/will
be undergoing for studying new FE and RO schemes
and algorithms to eventually include in the RO
chain for more sophisticated realtime processing
of data (cluster centroid, fast tracking etc).
Use of present CDF experience and ongoing LHC
developments. This work will be developed
within SiLC (PRC submission in May)