Reconfigurable Instruction Set Processors

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Reconfigurable Instruction Set Processors

• Francisco Barat
• Murali Jayapala
• Rudy Lauwereins

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Outline

• Motivation
• Reconfigurable Logic
• RISP
• Advantages
• Status
• past work
• future work
• Conclusion

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Motivation Typical MPEG-4 application
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iHome applications

• Properties of MPEG-4 applications
• Every object has its own decoder algorithm
• Scalable decoders
• Variable number of objects
• Interaction with user
• Decoder algorithm downloaded together with data
  SAOL/SASL, Java
• Decoder lasts longer than the standards future
  proof
• Conclusion
• much run-time flexibility is needed
• this leads to extensive use of Instruction Set
  Processors
• and dynamically reconfigurable hardware

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Motivation Processors

• Increase in Silicon Area
• Design Complexity - High
• Large design time
• Large design cost
• Flexibility vs Specialization
• Power hungry
• So there is a need for new
• Architectures
• Design tools (synthesis, compilers)

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Motivation RISP

• General purpose processors
• Very generic Instruction Set
• Application specific processors
• Very specialized Instruction Set
• For MPEG-4 kind, specialization to different
  application at runtime needed

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Reconfigurable Logic

• Large array of basic elements
• Dense interconnect
• Both reconfigurable

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Reconfigurable Logic
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Reconfigurable Logic
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Reconfigurable Processor
Microprocessor
Reconfigurable Logic
Reconfigurable Processor
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Processor coupling
Processor
Coprocessor
RFU
Memory
Bridge
Attached Processor
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RISP Block Diagram
Internal Memory
Processor core
Reconfigurable logic
Reconfigurable logic
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Advantages RISP

• The Runtime flexibility and specialization could
  be obtained
• Design Complexity reduced
• large area for reconfigurable logic
• design of reconfigurable logic simple -
  replication basic blocks
• less design time and cost
• From market point of view

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Crucial

• Existence of tools to aid the design
• Profilers, analyzers
• compilers
• simulators
• Most of the tools have to be developed to show
  the advantages in numbers

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Work so far

• Template architecture description
• The basic program flow
• configuration memory
• Reconfigurable logic
• from template architecture to an Instance
• Tools
• Compiler
• Instruction creation
• Instruction selection
• Initial work on Instruction set simulator

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Basic program flow
Fetch
Decode
Configuration Controller
Issue
Integer
Floating Point
Branch
Load/ Store
Reconfigurable Unit
Writeback
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Configuration Memory

• Configuration memory depends on
• granularity of basic elements
• density of configurable interconnect
• of reconfigurable logic
• Largely similar to the conventional program
  memory
• Configuration memory ? Instruction memory
• Configuration coding ? Instruction coding

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Configuration memory (contd)
. . . .

• One large instruction for a superscalar
  processor
• One VLIW word composed of instructions for the
• parallel units
• One Horizontal micro code
• Configuration memory ? Instruction memory

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Configuration memory (contd)
Encode
Decode
Configuration coding? Instruction coding
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Future work

• Template architecture description
• configuration memory hierarchy
• Reconfigurable logic
• granularity
• Interconnect
• Creation on function units on the fly
• Tools
• Architecture description language
• More on Compiler and Instruction set simulators
• Design flow
• Instantiation
• hardware synthesis
• Program compilation

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Conclusion

• Emerging multimedia applications need
• Runtime flexibility and specialization
• For the processors need
• low design cost and complexity
• Reconfigurable logic coupled with
  Microprocessors forming a RISP could be a good
  solution