Reconfigurable Instruction Set Processors: A Survey

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Reconfigurable Instruction Set Processors A
Survey

• Francisco Barat
• Rudy Lauwereins

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MMX example
?Ops
Evaluating MMX Technology Using DSP and
Multimedia Applications
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Outline

• Specialization
• Types of reconfigurable processors
• RISP architecture
• Evaluation

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Specialization of processors
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Instruction set selection
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Example of instruction reduction
Original
Specialized

• lsh d0, d0, 3
• sub d0, d0, 1
• lsh d0, 0xffff, d0
• or d0, d1, d0
• mul d0, 9632, d0
• mul d1, 6436, d1
• add d0, d1, d2
• sub d0, d1, d1
• mov d2, d0

• mask d0, d0, d1
• butt d0, d1

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Reconfigurable Processor
Microprocessor
Reconfigurable Logic
Reconfigurable Processor
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Processor coupling
Processor
Coprocessor
RFU
Memory
Bridge
Attached Processor
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Pipeline
Fetch
Decode
Configuration Controller
Issue
Integer
Floating Point
Branch
Load/ Store
Reconfigurable Unit
Writeback
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Instruction types

• Stream oriented
• Execute for a large number of cycles
• Typically a loop structure
• Many memory accesses, both reads and writes
• Register based
• Smaller latency
• Data comes mainly from registers and immediates
• Accesses to memory are usually restricted to one
  read or one write

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RISP Block Diagram
Internal Memory
Processor core
Reconfigurable logic
Reconfigurable logic
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A simple Reconfigurable Functional Unit (RFU)
Data Inputs
Reconfigurable Logic
Data Outputs
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The RFU as an address generator
Data Inputs
Reconfigurable Logic
Data Output
Address Output
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The RFU as a complex LD/ST unit
Data Inputs
Reconfigurable Logic
Address Output
Data
Data Output
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RFU with segments
Data Inputs
Segment 1
Segment 2
Configuration Controller
Segment 3
Segment 4
Data Output
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Configuration planes
Data Inputs
Reconfigurable Logic
Reconfigurable Logic
Reconfigurable Logic
Reconfigurable Logic
Data Outputs
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A more complex reconfiguration scheme
Data Inputs
Data Outputs
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Fixed opcodes
1111
ID
Reg1
Reg2
Imm
Dest1
Dest2
Register File
RFU
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Configurable opcodes
1111
ID
Param1
Param2
Param3
Param4
Param5
Register File
Translation
RFU
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Configuration unit
ID Address Model Segments
0 0x0000 RRI-R 012 1 0x0100 RR-RR 34 2 0x2800 RR
-R 3 0x3000 RI-R 567 4 0x7f00 RR-R 5 --- 6 -
-- 7 ---
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RISP qualitative evaluation

• Benefits
• Less number of instructions
• Specialized datapath
• Shared hardware
• Drawbacks
• Slower hardware
• More area
• More power consumption
• Difficult to use

Future will tell!!!