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CASI / ELEC 98
IEEE 1394
A high-speed computer I/O serial bus
By Rachad ALAO Ecole Nationale Supérieure des
Télécommunications ralao_at_venus.org
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Whats the best way to interconnect these devices
?
Video Camera
PC
DVD - RAM
IEEE 1394, by Rachad ALAO ( ralao_at_venus.org )
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Whats the best way to interconnect these devices
?
Isochronous Traffic. Bandwidth Requirement
6Mbit/s
Video Camera
PC
DVD - RAM
Sporadic traffic. Bandwidth Requirement 16Mbit/s

• Why not with USB? Too slow!
• Why not with a SCSI bus? Fast enough, but
• What about an IEEE 1394 bus? Youve got it!

IEEE 1394, by Rachad ALAO ( ralao_at_venus.org )
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IEEE 1394 Lecture Plan

• I. How does IEEE 1394 work ?
• Overview
• Topology
• Type of Transaction
• Protocols Structure
• Example of Data Transfer
• II. Architecture of a IEEE 1394 Controller.
• Project Overview
• Functional Block Overview
• Block Level Detailed Architecture
• Transaction Layer, driver.
• III. Conclusion.

IEEE 1394, by Rachad ALAO ( ralao_at_venus.org )
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How does IEEE 1394 work ? Overview

• High Speed
• Hot plug and play
• Isochronous capable
• Memory-bus-like logical architecture

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How does IEEE 1394 work ? Topology

• Physical topology is a non-cyclic network but
  Logical Topology is a bus.
• Node_ID 15 .. 0 Bus_ID15 .. 6
  Physical_ID 5 .. 0

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How does IEEE 1394 work ? Type of Transaction

• Different type of subaction
• Asynchronous subaction
• Asynchronous broadcast subaction
• Isochronous subaction

• Different part of a subaction
• Arbitration sequence
• Data packet
• Acknowledgment

Typical structure of a data packet
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How does IEEE 1394 work ? Protocols Structure

• Different managers needed
• ROOT ( Arbiter )
• CYCLE_MASTER
• ISOCHRONOUS MANAGER
• BUS MANAGER

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How does IEEE 1394 work ? Example of Data
Transfer 1
Video Camera
Node_ID 1
PC
DVD - RAM
Root Isochronous Manager Bus Manager Cycle
Master Node_ID 3
Node_ID 2
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How does IEEE 1394 work ? Example of Data
Transfer 2
DVD RAM want to perform a write data block
transaction to the PC
Isochronous Gap
Subaction Gap
Cycle_Start
Ch. i
Ch. j

• Step 1

Arbitration
TX_DATA_END
Cycle_Start
Ch. i
Ch. j
Data Packet

• Step 2, 3, 4

Acknowledge Gap

• Step 5

Cycle_Start
Ch. i
Ch. j
Data Packet
Acknowledge Packet
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How does IEEE 1394 work ? Example of Data
Transfer 3
Camera sends MPEG2 data to the PC at a 6 Mbit/s
fixed rate.

• Prior to all its isochronous transfers, the
  camera must allocates bandwidth and channel.

Isochronous Gap
Cycle_Start

• Step 1

Arbitration
TX_DATA_END
Cycle_Start
Ch. K Data Packet

• Step 2, 3, 4

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Architecture of a IEEE 1394 Controller Project
Overview
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Architecture of a IEEE 1394 Controller Functional
Block Overview
Receive
INT
Transmit_Granted
FIFO_DS
Hold
FIFO_R/W
Link_request
TPA
FIFO_Add7..0
Link_DS
Host_DS
FIFO_Data31..0
R/W
R/W
TPB
Link Layer
Phy Layer
Add7..0
Host_Add7..0
Link_DS
Local Host Bus Adapter
FIFO Controller
Link_Data7..0
Host_Data31..0
Link_R/W
Power
Phy_DS
FIFO_DS
Link_Add2..0
Phy_Data7..0
FIFO_Data31..0
Link_Data31..0
Clk ( 50 Mhz )
Clk ( 50 Mhz )
Link_On
Clk ( 33 Mhz )
/Reset
Power_Down
/Reset
/Reset
Local Bus Adapter Interface is Bus Dependent!
No generic interface can be given.
Transaction layer and part of the bus management
will be software components ( driver )
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Architecture of a IEEE 1394 Controller Block
Level Detailed Architecture - PHY
Receive
Transmit Data Encoder
Transmit_Granted
Hold
Link_request
TPA
Link_DS
Cable Analog Interface
Phy State Machine Internal Regs
R/W
Add7..0
TPB
Link_Data7..0
Phy_DS
Power
Phy_Data7..0
Clk ( 50 Mhz )
Receive Data Decoder
Link_On
Power_Down
/Reset
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Architecture of a IEEE 1394 Controller Block
Level Detailed Architecture - LINK
Receive
CRC
Transmit_Granted
Transmitter
FIFO_DS
Isoch. Manager
Hold
FIFO_R/W
Link_request
FIFO_Add7..0
Link_DS
FIFO_Data31..0
R/W
Link State Machine and Registers
Add7..0
Link_DS
Phy Interface
Link_Data7..0
Link_R/W
Link_Add2..0
Phy_DS
Phy_Data7..0
Link_Data31..0
Isoch. Monitor
Clk ( 50 Mhz )
Clk ( 50 Mhz )
Receiver
Link_On
/Reset
Power_Down
CRC
/Reset
IEEE 1394, by Rachad ALAO ( ralao_at_venus.org )
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Architecture of a IEEE 1394 Controller Block
Level Detailed Architecture - FIFO
INT
FIFO Controller Internal Regs
FIFO_DS
FIFO_R/W
FIFO_Add7..0
FIFO_Data31..0
Host_DS
R/W
Link_DS
Host_Add7..0
General Receive FIFO
Link_R/W
Host_Data31..0
Link_Add2..0
FIFO_DS
Link Layer Interface
Link_Data31..0
Host Adapter Interface
FIFO_Data31..0
Asynch. Transmit FIFO
Clk ( 50 Mhz )
/Reset
Clk ( 33 Mhz )
Isoch. Transmit FIFO
/Reset
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Architecture of a IEEE 1394 Controller Transaction
Layer, driver

• The Transaction layer and part of the bus
  management functions
• must be software components.
• Transaction layer must implement Read, Write and
  Lock transaction.
• Driver must offer ability to handle isochronous
  transfer.
• Driver must be IRQ driven and able to initiate
  DMA transfers.
• Driver model will depend on the target
  application OS.

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Conclusion

• Objectives
• Give a synthesis of the IEEE 1394 Bus standard
• Give a Hardware Specifications of an IEEE 1394
  Solution
• Constitute a good starting for the development
  of an IEEE 1394 Solution
• Reached !
• Gave me a good understanding of the IEEE 1394
  Protocol
• - Showed me the difficulty to build
  specifications from a complex standard
• - No multicast for asynchronous packets!
  Surprising for such a complicated
• standard.

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