Novel Communications Mechanisms

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Novel Communications Mechanisms Optical
Interconnection
Task Leaders L. C. Kimerling, MIT and D. A. B.
Miller, Stanford
Other principal investigators E. A. Fitzgerald,
MIT J. S. Harris, Stanford J. M. Ballantyne,
Cornell P. Krusius, Cornell P. Persans, RPI
On-chip optical waveguides, modulators and
detectors for photonic clock distribution, data
communication and wavelength division
multiplexing and microwave RF techniques to
enhance chip I/O bandwidth.
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ANALYSIS OF OPTICAL INTERCONNECT OPPORTUNITIES
D. A. B. Miller, Ginzton Lab, Stanford
OBJECTIVE To establish which interconnect
functions are best performed optically how best
to perform them

• MILESTONES
• Define target performance metrics for
  optoelectronic devices and optics.
• Identify implementation path for key functions.

APPROACH Analyze, clock distribution, on-chip
interconnects and off-chip interconnects for
device options (lasers, modulators,
photodetectors) optics options (free-space,
fibers, waveguides) CMOS driver and receiver
circuit issues (power, crosstalk, latency)
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Compute BW
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Comp BW
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Electrical I/O BW
Elec I/O BW
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I/O BW
Optical I/O BW
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Compute Bandwidth (Gbit/s) Gates x
Clock-Speed
I/O Bandwidth (Gbit/s) I/Os x Clock-Speed
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SIA Predictions
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Line width (microns)
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SILICON MICROPHOTONICS TECHNOLOGY
L.C. Kimerling, MIT Materials Processing Center

• OBJECTIVE
• To establish an IC compatible process technology
  for integration of photonic interconnection with
  silicon electronics.
• low cost, high yield
• low power dissipation
• high bandwidth
• reduced interconnection density

• MILESTONES
• SiEr LED
• PolySi nanowaveguide
• Integrated CMOS driver/modulator
• Si microresonator devices
• 16x fanout clock signal
• Integrated Optical Data Link

APPROACH To create technology building blocks
under the constraints of conventional fabline, IC
design and systems performance requirements.
SiEr emitter/waveguide structures Si/SiO2
waveguide/modulator/couplers SiGe detectors
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III-V on SILICON TECHNOLOGYE.A. Fitzgerald,
MIT Materials Processing Center

• OBJECTIVE
• To establish an IC compatible, monolithic process
  technology for integration of III-V
  optoelectronic devices with Si CMOS
• low cost, high yield
• low power dissipation
• high bandwidth
• reduced interconnection density

MILESTONES III-V LEDs and lasers on Si Creation
of a relaxed SiGe/Si co-planar substrate
technology III-V LEDs and lasers on such
co-planar substrates Demonstration of optical
links on Si
APPROACH To create III-V LEDs and lasers on Si
substrates using intermediate SiGe interlayers.
GaAs and InGaAs emitters on Ge/SiGe/Si
substrates development of co-planar SiGe/Si
technology useful for both III-V integration and
SiGe detector integration
co-planar SiGe/Si
GaAs on Si
Ge
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HYBRID INTEGRATION OF III-V DEVICES ON SILICONJ.
S. Harris and D. A. B. Miller, Stanford Solid
State and Photonics Lab
MILESTONES Demonstration of dense array optical
interconnects with bonding to active CMOS
circuits optimized devices optimized circuit
designs

• OBJECTIVE
• To establish the viability of integration of
  optoelectronic devices with finished Si CMOS
  circuits through research in
• integration processes
• devices compatible with integration
• operating with CMOS voltages and clock speeds

APPROACH Investigate solder bonding
alternative hybrid integration techniques
optimized devices compatible with CMOS circuit
drive (e.g., improved modulators,
detectors) Assess performance of entire link
skew, jitter, latency, power, error rate and
deduce limitations to performance
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PARALLEL ARRAY TECHNOLOGIES
J. M. Ballantyne and P. Krusius, Electrical
Engineering, Cornell
MILESTONES
OBJECTIVE
To demonstrate the feasibility of on chip multi-
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Monolithic, wavelength selective materials and
MEMS devices.
wavelength sources and detectors for
multiplexed I/O.
Microamp quantum dot VCSEL arrays.
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Integrated III-V laser/CMOS transmitter.
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APPROACH
Functional microphotonic devices for routing/
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reconditioning signals.
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Wavelength multiplexed, on-chip detectors and
VCSEL lasers.
Efficient,
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-selective, monolithic receivers
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GaInP S-K islands with Si lattice constant
Si heteroepitaxy of selective, quantum dot
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active regions for detectors and lasers.
Demonstrate CMOS process compatibility of
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monolithic III-V device materials.
Demonstrate III-V emitter/detectors for
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multiplexed communications.
,
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NOVEL WAVEGUIDES FOR OPTICAL INTERCONNECTSP. D.
Persans, J. Plawsky, X.-C. ZhangRPI

• OBJECTIVE
• Develop waveguide materials and processing
  approaches for on-chip and MCM optical
  interconnects.
• APPROACH
• Fabricate passive waveguide structures including
  horizontal and vertical input and output couplers
  and bends, and straight-line waveguides using IC
  process compatible polymers and inorganics.

• Focus on large area processing techniques and
  materials photosensitive fluorinated polymers,
  reactive ion etching, sputtering.
• Focus on off-chip light sources with on-chip
  modulators.
• MILESTONES
• Development of test structures
• Deposition and patterning of photosensitive
  polymers.

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Approaches 1. Analyze approaches and define
likelihood of success. 2. Evaluate optical chip
I/O and clock distribution functions. 3.
Develop CAD tools for device design, component
integration and partitioning of
optics/electronics. 4. Develop materials and
processes for integration on silicon. 5.
Prototype hybrid and monolithic architectural
platforms, and assess the limits of performance
and integration. 6. Develop entry-level
functionality for e-test and MCMs.
Objectives 1. Complete technical analysis of
optical interconnection with design criteria for
speed/power/area tradeoff. 2. Evaluation of
waveguide and free space performance. 3.
Design-stabilized prototypes for early entry
applications such as testing and MCM/PWB
functions. 4. Monolithic and hybrid prototypes
to evaluate performance, process compatibility
and cost. 5. Novel architectures free space
and optical buss prototypes. 6. Demonstration
of GHz clock and data distribution functions.