Introduction to the architecture of Origin 2000

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Introduction to the architecture of Origin 2000
3000

• Presented by Liang Shi
• CSCI 8140, CS, UGA
• Instructor Dr. Taha

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Outline

• The architecture of O2K (CASC,KU)
• -SSMP and CC-NUMA
• -The node board
• -Interconnecting nodes-Hypercube
• -Cache Coherence Virtual memory
• -Scalability Latencies and Bandwidths
• Features of O3K

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O2K-SSMP, CC-NUMA

• Designed as the successor of the SGI SMP in
  September 1998
• A Scalable Shared-Memory Processor (SSMP) system
• An instantiation of a Cache-Coherent Non-Uniform
  Memory Access (CC-NUMA) Architecture
• Taking Advantage of both shared-memory systems
  and distributed computing systems

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O2K-system structure

• Two CPUs are connected through a "hub" to a
  memory to form a "node"
• multiple nodes are connected using an
  interconnection network to form a complete Origin
  system
• The distributed memories are seen as a single
  (logical) memory space, and any processor can
  access any memory location.

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O2K-node diagram(2-16 CPUs)
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O2K-The node board

• A node supports both distributed virtual memory
  and distributed cache.
• The hub is basically a multi-port crossbar
  connecting
• the CPU subsystem,
• the memory subsystem at 780MB/sec (600MB/sec
  effectively),
• the I/O subsystem, and
• the external routing network at 780MB/sec
  (624MB/sec effectively).

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O2k- Interconnecting nodes

• Multiple processors can work on the same problem.
  Multiple distributed memories appear as a single
  physical memory, underlying a single
  virtual-memory address space
• Built around a CrayLink router network, where
  each node can be connected to a CrayLink router
  and that router can be connected to other nodes
  or other routers or both.

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O2K - 32 Processors
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O2K - 64 Processors
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O2K 128 Processors
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O2K- Directory Cache Coherence

• Two other CC
• -Bus-based multiprocessor architectures listen
  to all memory access activity (snoop)
• -Broadcast, but does not scale.
• Directory-based cache coherence
• -Memory is organized into cache lines.
• -Hub initiates the memory fetch of cache
  lines.
• -If a CPU wants to modify a cache line, it
  must gain exclusive ownership, sending
  invalidation.
• -Coherency traffic only grows proportionally
  with the number of nodes, allow to scale.

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O2K- Virtual memory

• Improve the cost-efficiency of main memory
• If no room for a new page, an old page is written
  back to the paging disk , a new page may be moved
  to memory from disk
• Minimize "page swapping
• Much more Complicated in O2K
• Rules the process using the page holding that
  data must be running on a CPU as close as
  possible to the node containing that page, and
  that node must be uncongested.

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O2K-Scalability Latencies and Bandwidths
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O3K System Architecture

• Launched in July, 2000
• CC-NUMA with up to 512 processors (Planned up to
  4092)
• Directory Based cache coherence
• Broad spectrum of application areas
• 4 way processing nodes
• All memory and IO is globally accessible
• All major programming models are supported.

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O3K - Bricks

• Building blocks called bricks
• C-brick processor module
• R-brick routing brick connecting C-bricks
• I-brick Base IO with PCI and USB slots
• P-brick PCI extension
• X-brick High-performance IO extension
• G-brick, D-brick, Power Bay

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O3K Architecture Diagram
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O3K- SGI 3000 Family overview
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O3K C-brick, R-brick
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Reference

• www.ku.edu/acs/docs/other/sgi-short-intro/index.s
  html
• www.nus.edu.sg/Major/SVU/publications/
  SVULink/vol_1_iss_1/ccNUMA.html
• www.oscinfo.osc.edu/training/o2k/o2k_new/fsld.027.
  html
• www.sgi.com/origin/3000/
• wwwbode.cs.tum.edu/gerndt/home/Teaching/scalable_
  shared_memory_systems/ Kapitel7-1.pdf

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Thank you!