Overview

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Overview

• CAN Bus System
• PIC Micro-controllers
• Synthesis System
• One or two details
• Experience
• Demo (perhaps)
• Conclusions

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Aims

• Compile a CPU-based CAN node into a hardwired,
  minimal circuit.
• Eliminate all redundant registers and pipeline
  stages arising from CPU-based origin
• Also, to explore scalability of BDDs for real
  designs!

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CAN Bus
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CAN NODE
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PIC 12c671
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CAN ROM Firmware
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Firmware -gt BDD
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ISS Coding

• Captured in C Preprocessor Macros.
• A glorified RTL
• (g) ? ab exp
• (altlt5)(b31) exp
• Register and memory maps hand-coded XML.
• Added FAULT reg to trap invalid instructions.
• Added GUTTER reg to collect mis-directed writes.
• Five declarations, resolved with priority reset,
  interrupt, decode, PC advance, resting.

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General Project Flow

• Read In PIC Chip Designation
• Instruction set description
• On-chip register file description.
• Read in Compiled Firmware.
• Read in RTL for MAC (PHY is a wired-or).
• Flatten everything to monster BDD.
• Save, Load, Check or otherwise manipulate.
• Write out new synthesisable Verilog RTL design.

Annotate observable state
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Non-det simulation

• BDD version of NSF trivial walk yields SAT.
• Some vars have 'current state' so not so
  trivial backtracking required.
• Record branches taken unset (primed) vars.
• Commit primed vars back to non-primed, advance
  tnow, then start a new cycle.
• Got 'stuck' on illegal writes or instructions.
• Non-deterministic where there is true choice.

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Clock Cycle Reduction
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State Bisim (BoualiSimone)
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State Bisim C Version
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Lane Collate - Vectorise

• State bi-sim gives only a partition relation
• Need to chose an encoding for it
• Currently just delete all flip flops not in
  support.
• Logic scanned for sub-expressions
• Build network of nodes
• Each nodes is leaf, AND, XOR, Mux2, FullAdder
• Links invert or not
• Collate similar bit lanes to form a word op and
  hence a new encoding.

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Screenshot Timing Diagram
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Demo

• All is currently working except
• - MAC Netlist not yet included
• - Temporal Bisim Bug
• - Full-sized design takes too long!

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Conclusions about BDDs

• My BDD order has primed locked adjacent to
  non-primed bad idea ?
• BDD ordering is too hard to find in general
• BDD makes little use of address decode and none
  of ALU width.
• Use a non-unique representation that follows
  structure of input AST's and be prepared to do
  some dynamic equivalence checking as needed.

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Conclusion Overall

• System must be decomposed into smaller parts for
  BDD analysis or else use a totally different
  approach (e.g. symbolic state trajectory).