Ch. 2: Sequential Circuit Design

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Ch. 2 Sequential Circuit Design

• Block Diagram for a General Sequential Circuit

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• Types of Sequential Circuits
• Asynchronous sequential
• State is permitted to change at any time
• Synchronous sequential
• State is permitted to change only at times
  specified by a clock signal
• Memory Devices
• Asynchronous sequential circuits
• Delay element, wire delay, latch, flip-flop
• Synchronous sequential circuits
• Latch level-triggered device (typical usage)
• Flip-Flop edge-triggered device (typical usage)

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Basic S-R Latch Design
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Enabled S-R Latch Design
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D-Latch Design
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D Flip-Flop, Master-Slave Device
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J-K Flip-Flop
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Hazards (due to Races)
Static Hazard
Dynamic Hazard
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Elimination of Hazards
add consensus term
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Metastability

• Metastable signals can occur due to unstable data
  values during clock signal transitions
• Ex

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Solutions to Metastability

• Metastability can never be completely eliminated
• Try to reduce the likelihood of metastable values
• Possible solutions for asynchronous data inputs
• Use data inputs with extremely fast transitions
• Buffer data through several flip-flops before
  using them

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Synchronous Sequential Circuit Design

• Typically based on Finite State Machines (FSMs)
• Mealy machine
• Outputs depend on the present inputs and the
  current state
• Moore machine
• Outputs depend on the current state only
• FSM Design Steps(1) Draw a state diagram (or
  state table)(2) Make a state assignment(3)
  Derive a state transition table(4) Derive logic
  equations(5) Derive logic diagram from the logic
  equations

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Counter Example (Prob. 2-16)

• 3-bit synchronous binary counter using D FFs
• Step (1) State Diagram

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• Step (2) State Assignment
• Use variables (A,B,C) and 3-bit binary assignment
• Step (3) State Transition Table

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• Step (4) Derivation of Next State Equations

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• Step (5) Logic Diagram

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Sequence Detector (Prob. 2-22)

• Design sequence detector (for 1101) using J-K FF
• Step (1) State Diagram

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• Steps (2) and (3) State Assignment State
  Transition Table

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• Step (4) Derivation of Next State and Output
  Equations

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• Step (5) Logic Diagram

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Sequential MSI Devices

• n-bit Register
• Shift Register

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• Universal Shift Register
• Binary Ripple Counter

Timing Diagram (important)