A 12b 75MSs Pipelined ADC using OpenLoop Residue Amplification - PowerPoint PPT Presentation
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A 12b 75MSs Pipelined ADC using OpenLoop Residue Amplification
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Real time post-processor off-chip (FPGA) Die Micrograph (7.9mm2) ... Processor. Properties ... Post-Processor. Stage1 Implementation. Layout ... – PowerPoint PPT presentation
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Title: A 12b 75MSs Pipelined ADC using OpenLoop Residue Amplification
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A 12b 75MS/s Pipelined ADC using Open-Loop
Residue Amplification
- Boris Murmann
- Bernhard E. Boser
- University of California, Berkeley
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Outline
- Highlights
- Objective Approach
- Key Results
- Implementation Details
- Open-Loop Residue Amplification
- Errors Correction Mechanism
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Conventional Pipeline Stage
- Need high speed, low noise, high gain OTA
- Dominates stage power dissipation
- Hard to implement in deep sub-µm technology
- High gain ? power inefficient topologies
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Design Objective
- Power efficient, improved sub-µm compatibility
- Need to restore benefits of electronic feedback
- Linearization Digital arithmetic
- Desensitization Digital background
calibration Biasing layout techniques
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Evaluation Prototype
- Re-used ADC in 0.35µm Kelly, ISSCC 2001
- Modified only 3beff stage1 ? open-loop
- Conventional 9beff backend, 2 redundant bits
- Real time post-processor off-chip (FPGA)
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Die Micrograph (7.9mm2)
LOGIC
CLK
REFERENCE AND B IAS
PIPELINE BACKEND
STAGE1
SHA
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Stage1 Amplifier Power
- ? Same noise and settling time
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Measured INL
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Measured INL
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INL Zoom (Post-Proc. ON)
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FFT Plot (fs75MHz, fin40MHz)
Post-Proc. Off SNR48dB THD-50dB SFDR58dB
Post-Proc. On SNR67dB THD-74dB SFDR76dB
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Performance Summary
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Stage1 Residue Amplification
- Design parameter VOVVGS-VTH
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Choice of VOV
- First order analysis using Taylor expansion
Mismatch
Gain Compression
Linear
- Large VOV ? Small nonlinearity errors
- Tradeoff Relative increase in ISS to maintain
required Gm ? ISS/VOV - Goal Choose VOV reasonably large to yield
compact, low order amplifier model
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Errors as Function of VOV
Error
VOV V
- Error budget ½ LSB of 9b backend ? 0.1
- VOV gt 250mV ? 5th and higher order negligible
- Achieved ??/? lt 0.3 ? 2nd order negligible
- 3rd order practically unavoidable
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Stage1 Model with Errors
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Nonlinear Error Correction
- Invert amplifier polynomial
- Express error as function of VRES1
- Push error into digital domain through backend
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Nonlinear Error Correction
- Pre-computed 2-D look-up table, compressible
- ? 64kBit ROM covers processtemp. variations
- Problem How to determine optimum p2?
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Redundant Residue Mode
- Both residues can be used for conversions
- Requires extra DAC states and comparators
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Residue Segment Zoom
- Gain compressive segments
- Optimum p2 digitally maps onto straight lines
- Idea Measure h1 and h2, adjust p2 until h2h1
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Distance Estimation
- RNG decides top/bottom, independent of VIN1
- Count codes ? q in bottom channel ? Reference
count n
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Distance Estimation
- Counter array in top channel
- Find closest match to n ? H1
- H1 is unbiased estimate of true distance h1
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Complete Post-Processor
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Properties
- Background calibration, parameters track without
interrupting ADC operation - Relies on busy ADC input gt1/16 FS. Invalid
estimates detectable ? discard - Tradeoff Tracking speed vs. accuracy
- This work ?LMS?100...200ms, sufficient to track
e.g. Tambient - Address faster variations on circuit level
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Post-Processor Hardware
- 8400 Gates, 64 bytes RAM, 64kBit ROM
- Implementation in 0.35µm technology
Area1.4mm2 (18)
Power10.5mW (3.6)
Post-Processor
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Stage1 Implementation
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Layout Circuit Techniques
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Parameter Tracking
- GmR replica bias desensitizes, loosens tracking
requirements in LMS loops
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Summary
- First published calibration technique to address
residue amplifier nonlinearity - Enables open-loop residue amplification
- Power efficient
- Improved deep sub-µm compatibility
- Judicious combination of digital and analog
techniques ? feasible, low overhead solution - Future potential, deep-sub-µm Pdigital?
Panalog? ? increasing power savings
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