An ASIP Design Methodology for Embedded Systems

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An ASIP Design Methodology for Embedded Systems
K. Kucukcakar, in Proc. the 17th Int'l Workshop
on Hardware/Software Codesign, 1999.

• Cheong Ghil Kim

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Contents

• Introduction
• Related Work
• Approach
• Results
• Conclusion Future Directions

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Introduction (1/2)

• Application Specific Instruction-Set Processor
  (ASIP)
• An alternate processor design method for
  dramatically changing computing environment.
• More flexibility than ASICs
• Smaller silicon area than GPPs.
• Some overhead for all other applications
• ASIP design task
• Creation of a new processor
• Whose instruction set and architecture are
  customized for a targeted set of applications.

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Introduction (2/2)

• Goals for this paper
• A unique architecture and methodology to design
  ASIPs in the embedded controller domain.
• System efficiency stays acceptable for embedded
  systems.
• Cost, code size, performance, and power
• Customization should be as local as possible.
• Changes to the software environment should be as
  minimal as possible.
• Backward compatibility for the bulk of the
  software should be preserved.
• Variable degrees of manufacturing flexibility is
  possible
• Custom
• Mask programmable
• Field programmable

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Related Work (1/3)

• Scope
• Custom processor design
• MC68HC12 and DSP
• Combination of
• Instruction-set definition
• Architecture creation
• Instruction mapping onto a newly created
  architecture
• Instruction-set architecture design
• Pass the software through a profiler which
  provides an importance factor for each
  operation.
• Architecture consists of
• A kernel primitive RTL operators, register file,
  multiplexers, control, and buses
• Application specific ALU
• Simple and restrictive

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Related Work (2/3)

• Instruction-set definition instruction
  selection
• An analysis tool is used to extract operations
  and operations sequences from an application.
• Instruction-set description in mML
• Datapath parts creation by manual
• Operations are bundled to create instruction
  formats.
• Instruction-set architecture design
  instruction mapping from an application and
  architecture template
• Architecture template defines the pipeline
  structure which consists of fetch, decode,
  register read, ALU operation, memory access and
  register write phases

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Related Work (3/3)

• Approaches given above
• Tuning for a set of application
• A new instruction set
• A new architecture
• Problems
• Create extreme fluidity in the processor
• Require very effective hardware synthesis and
  retargetable software compilers
• Ignore control aspect of design

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Approach (1/5)

• Customizing an existing processor (proposed
  method)

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Approach (2/5)

• Design flow
• A software implementation using traditional
  methods
• Performance bottlenecks are identified with the
  aid of a profiler program
• The processor is customized through addition of
  applicaion-specific instructions.
• The firmware is updated to use new instructions

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Approach (3/5)

• Identification of new instructions
• Frequently used subroutines in the firmware
• Device drivers
• Basic elements of computation
• Timer operations
• Operating system primitives such as schedulers
• Sequences of common instructions in the
  application
• Shift-and-add sequence
• Zero-overhead loops
• Data type conversion
• Data formatting for I/O
• Signal polling

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Approach (4/5)

• Processor architecture
• A fixed set of instructions datapath new
  control and datapath logic through use of
  programmable hardware
• Characteristics
• Applicable to most industrial processors
• Programmable logic reduce the time-to-market
• Lack of efficient access to processor internals
• Static decode architecture
• New instructions a set of predetermined opcodes
• Fetched and decoded by processor
• Processor relinquish the control of datapath to
  the programmable section
• Dynamic decode architecture
• New instructions defined per application basis
• Decoding is performed by the programmable logic
• Processor sends a signal to the programmable
  logic section

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Approach (5/5)

• ASIP implementation
• RTL synthesis
• Behavioral synthesis
• Reuse of code segments from existing instructions
  in definition of the new instructions
• Easy partitioning of new instruction logic from
  the existing implementation
• Firmware modification
• Assembly code
• Addition to compiler
• Retargetable compilers

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Results (1/2)

• Hex-to-binary conversion example
• Control oriented operation
• 75 reduction in the number of cycles by
  eliminating
• Unnecessary instruction fetching
• Data passing between instructions
• Creating unused information
• Program memory reduction 39 bytes to 1 byte

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Results (2/2)

• 16 16 multiply example
• Not a control oriented operation (mostly
  shift-and add multiplication)
• 3 different instruction implementation
• A exploits a programmable control section with
  no datapath extension
• B add an 88 single-cycle hardware multiplier
• C addition of eight-location register file
• Program memory reduction 51 bytes to 1 byte

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Conclusion Future Directions

• ASIP architecture co-design methodology to
  improve the performance of embedded system
  application through instruction-set
  customization.
• Demonstrate the significant benefits on control
  and data oriented applications.
• More automation in the methodology would enable
  automatic HW/SW partitioning capability.