Shift Registers

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Shift Registers

• Lecture L8.6v
• (Verilog)
• Section 8.3

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4-Bit Shift Register
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shift4.v
module ShiftReg(clk,clr,data_in,Q) input
clk input clr input data_in
output 30 Q reg 30 Q // 4-bit
Shift Register always _at_(posedge clk or posedge
clr) begin if(clr 1) Q lt 0
else begin Q3 lt data_in Q20 lt
Q31 end end endmodule
Note non-blocking assignment
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shift4 simulation
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Ring Counter
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ring4.v
module ring4(clk,clr,Q) input clk
input clr output 30 Q reg 30
Q // 4-bit Ring Counter always _at_(posedge clk
or posedge clr) begin if(clr 1) Q lt
1 else begin Q3 lt Q0 Q20
lt Q31 end end endmodule
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ring4 simulation
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Johnson Counter
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johnson4.v
module johnson4(clk,clr,Q) input clk
input clr output 30 Q reg 30
Q // 4-bit Johnson Counter always _at_(posedge
clk or posedge clr) begin if(clr 1) Q
lt 0 else begin Q3 lt Q0
Q20 lt Q31 end end endmodule
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Johnson Counter
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A Random Number Generator
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Q3 Q2 Q1 Q0 0 0 0 1 1 1 0 0 0 8 1 1 0 0 C 1 1
1 0 E 1 1 1 1 F 0 1 1 1 7 1 0 1 1 B 0 1 0 1
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Q3 Q2 Q1 Q0 1 0 1 0 A 1 1 0 1 D 0 1 1 0 6 0 0
1 1 3 1 0 0 1 9 0 1 0 0 4 0 0 1 0 2 0 0 0 1 1
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rand4.v
module rand4(clk,clr,Q) input clk
input clr output 30 Q reg 30
Q // 4-bit Random number generator always
_at_(posedge clk or posedge clr) begin if(clr
1) Q lt 1 else begin Q3 lt Q3
Q0 Q20 lt Q31 end end endmodule
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A Random Number Generator
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Clock Pulse
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clk_pulse.v
module clk_pulse(clk,clr,inp,outp) input
clk input clr input inp output
outp wire outp reg 20 Q //
clock pulse generator always _at_(posedge clk or
posedge clr) begin if(clr 1) Q lt 0
else begin Q2 lt inp Q10 lt
Q21 end end assign outp Q2 Q1
Q0 endmodule
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