ANNOUNCEMENTS

1
Lecture 39

• ANNOUNCEMENTS
• Late projects will be accepted
• by 110PM Monday 4/30 20 pt penalty
• by 110PM Friday 5/4 50 pt penalty
• Extra office hour with Frank today 3-4PM in 382
  Cory
• Quiz 6 Review Session this Friday?
• OUTLINE
• The MOSFET
• Sub-threshold leakage current
• Gate-length scaling

2
Sub-Threshold Leakage Current

• We had previously assumed that there is no
  channel current when VGS lt VT. This is
  incorrect.
• If fS gt fF, there is some inversion charge at
  the surface, which gives rise to sub-threshold
  current flowing between the source and drain

3
Sub-Threshold Slope S
4
How to minimize S?
5
MOSFET Scaling

• MOSFETs have scaled in size over time
• 1970s 10 mm
• Today 50 nm
• Reasons
• Speed
• Density

6
Benefit of Transistor Scaling

• IDS ? as L ? (decreased effective R)
• Gate area ? as L ? (decreased load C)
• Therefore, RC ? (implies faster switch)

7
Circuit Example CMOS Inverter
8
td is reduced by increasing IDsat
9
Constant-Field Scaling

• Voltages and MOSFET dimensions are scaled by the
  same factor kgt1, so that the electric field
  remains unchanged

10
Constant-Field Scaling (cont.)

• Circuit speed
• improves by k
• Power dissipation
• per function
• is reduced by k2

11
VT Design Trade-Off

• Low VT is desirable for high ON current
• IDsat ? (VDD - VT)? 1 lt ? lt 2
• But high VT is needed for low OFF current

log IDS
Low VT

• VT cannot be scaled
• aggressively!

High VT
IOFF,low VT
IOFF,high VT
VGS
0
12

• Since VT cannot be scaled down aggressively, the
  power-supply voltage (VDD) has not been scaled
  down in proportion to the MOSFET channel length

13
Generalized Scaling

• Electric field intensity increases by a factor
  agt1
• Nbody must be scaled up by a to control
  short-channel effects

• Reliability and
• power density
• are issues

14
CMOS Scaling and the Power Crisis
1E03
Active Power Density
1E02
1E01
1E00
Power (W/cm2)
1E-01
1E-02
Passive Power Density
1E-03
1E-04
1E-05
0.01
0.1
1
Gate Length (µm)

• Lg/VDD/VT trends ? increases in
• Active Power Density (?VDD2)
  1.3X/generation
• Passive Power Density (?VDD) 3X/generation
• Gate Leakage Power Density gt4X/generation

Source B. Meyerson, IBM, Semico Conf., January
2004