Presentation Title Arial Bold 32pt

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Electrodeposited Photoresists for Wafer
Applications
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Nature of ED Resists

• ED stands for electrodeposited
• ED paint used by Ford since 1960
• Emulsion of photoresist Micelles in water
• - 50 150 microns
• - Micelles contain the
• resist components
• - Micelles have a
• or - charge

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Conformation on 3-D Structures
Deposits on all conductive surfaces
Intervia 3D-P over thick plated copper
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Dow Electronic Materials ED Resists

• Intervia 3D-N
• Negative tone image / cathodic wafer
• (wafer has negative charge)
• Intervia 3D-P
• Positive-tone image / anodic wafer
• (wafer has positive charge)

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Intervia 3D-N Coating Process
Micelles migrate to cathodic substrate

H2
O2
H2O
RCO2-
Inert Anode
Conductive Wafer (Cathode)
RCO2-
NR3
NR3
NR3
NR3
RCO2-
NR3
NR3
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Self Limiting Behavior
resist
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Deposition Current Profile
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Intervia 3D-P Application Process

• Resist Coating
• - Coating Cycle
• . 100 - 300 V DC
• . 10 ASF peak
• . Potential applied for 10 - 20 seconds
• - Thickness Control
• . Temperature
• . Solvent
• Exposure 365 - 405 nm

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Thickness vs. Temperature
Thickness vs. Temperature
Thickness (microns)
Temperature (ºC)
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Deposit Uniformity
Thickness Uniformity
Thickness (microns)
Position
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ED Resist Comparison

• Intervia 3D-N
• Negative working
• 6 100 µm final thickness
• 200-300 mJ/cm2 _at_365nm
• Organic acid develop / strip
• Acid and alkaline etches
• Resistant to many plating chemistries

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ED Resist Comparison

• Intervia 3D-N
• Negative working
• 6 - 100 µm final thickness
• 200-300 mJ/cm2 _at_365nm
• Organic acid develop / strip
• Acid and alkaline etches
• Resistant to many plating chemistries

• Intervia 3D-P
• Positive working
• 6 µm target final thickness
• 250-400 mJ/cm2 _at_405nm
• -CO3,-OH or TMAH develop
• Plating and acid etching
• Hydroxide or organic solvents

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Tools
ED Resist Coater for RD and Low Volume
Production
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Problems with Spin-on Resists

• 100µm feature spin coated with 6.0 µm of
  photoresist.
• Little or no coverage on outside corners
• Very thick coverage in inside corners and at
  bottom of the feature

Image of 25µm lines patterned over the top of
45µm wide features
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Coated Wafer Structures
SEM image showing 5µm of electrophoretic
photoresist deposited over a 300µm deep trench.
SEM image of 6µm of electrophoretic photoresist
deposited over a series of 92µm tall features.
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Examples of Wafer Processes Using Intervia ED
Resists
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Basic 3-D Test Structures
source Meco
Sketch of proposed technology for wafer-through
hole interconnects
Set of 10, 20, 30 40 µm wide test slits
reproduced at 150µm deep cavity
SEM Source Meco
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Ni Plated Structures on Polyimide
SEM photomicrographics of conformally
electroplated Ni lines across polyimide grooves
using Intervia 3D-P electrodeposition
Source Dow Electronic Materials
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ShellCase Process
ShellOP for Image Sensors and Light Detection
Devices

• Dow ED Products
• Negative ED photoresist
• Developer
• Remover

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Etching Conductive Vias with ED Resists
a) Photolithography on thick resist b)
Through-wafer etching (HDLP RIE) c) Thermal
oxidation and polysilicon deposition (LPCVD) d)
CVD metallization (W or Cu) and
electro-plating (Cu only) e) Electrodeposited
resist deposition f) Resist patterning by photo
lithography g) Metal and polysilicon etching h)
Photoresist removal
e)
a)
f)
b)
g)
c)
h)
d)
Source Quate Group, Stanford University
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Backside Contacts
SEM micrograph of final through-wafer vias
Source Lindedre, Baltes, Gnaednger
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Backside Contacts
through-hole sidewall
SEM micrograph showing metallization on 111
sidewalls for elimination of uncontrolled light
reflections.
Source Lindedre, Baltes, Gnaednger
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Philips Thru Via Imaging
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Philips Thru Via Imaging
Quadruple leads in a single through-wafer hole
and a toroid structure
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Exposure Using Phase Gratings
Schematic view of 3-D exposure using phase
gratings
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Plated Coils
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Infineon ELASTec Wafer Level Bumping
Intervia 3D-P Resist
Finished Bump
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ELASTec Process Steps
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Elastic
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Silicon Optical Bench
2-D Diagram of SiOB-I. Number 1, 2 3 indicate
the regions where cross sections are taken for
the fabrication diagrams.
Design II Interconnect Partially shielded
microstrip. (All dimensions are in microns)
Source Banerjee, Drayton
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Impact of Resist Tone on Printed Defects
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Intervia 3D-N Typical Application Process
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Intervia 3D-N Application Process

• Chemical Clean
• Preposit Cleaner 742
• Sulfuric acid based soak cleaner
• Removes fingerprints soils
• 50 - 55 degrees C
• 2 - 3 minutes

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Intervia 3D-N Application Process

• Chemical Clean
• Preposit Etch 748
• Monopersulfate etchant
• Micro roughens copper (0.5 - 1.0 µm)
• 30C
• 2 - 3 minutes

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Intervia 3D-N Application Process

• Resist Coating
• Resist is sparged upon entry to fully wet the
  part
• Vibration of parts may be used in some
  applications to release air bubbles
• Part to be coated is the cathode
• Stainless steel anodes

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Intervia 3D-N Coating Cycle
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Intervia 3D-N Coating Cell
Vibrator
Spargers
SS Anode
Part to be Coated
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Intervia 3D-N Application Process

• Resist Coating
• Coating Cycle
• 100 - 300 V DC
• 10 ASF peak
• Potential applied for 10 - 20 seconds
• Thickness Control
• Temperature
• Coating Time
• Voltage

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Typical Tmin Curve for Intervia 3D-N
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Intervia 3D-N Application Process

• Conservation Rinse
• Reclaims resist drag-out
• Conservation resist is ultrafiltered to reclaim
  solids
• D.I. Final Rinse

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Intervia 3D-N Topcoat

• Contains cellulose-based material in water
• Reduces tack of coating
• Reduces edge recession
• Dissolves quickly during development step

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Intervia 3D-N Application Process

• Air knives
• Remove bulk moisture
• Promotes uniform drying
• Convection Dry
• 105C
• 10 minutes

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Intervia 3D-N Application Process

• Exposure
• 300 mJ/cm2 required at 5 micron resist thickness
• 365 nm peak
• Intensity affects required dose
• Subject to Low Intensity Reciprocity Law Failure
  (LIRLF)
• 10 mW/cm2 minimum recommended

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Intervia 3D-N Application Process

• Development
• Intervia 3D-N Developer
• 38 - 42C
• Clear time 30 - 120 seconds
• 50 breakpoint

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Intervia 3D-N Application Process

• Plating
• Cupronal BP (copper)
• Auronal BP (gold)
• Solderon BP ( tin lead, lead free, low alpha
  lead)
• Nikal BP (nickel)
• Etching
• Cupric Chloride
• Ferric Chloride

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Intervia 3D-N Application Process

• Stripping
• Intervia 3D-N Remover
• 50 - 65C

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Microfabrication Capabilities

• Etched features with 0.2 um tolerances
• Deep (through-wafer) etching
• Contoured plated features (photoresists and
  metals)
• Submicron multilayer feature-to-feature alignment
• Submicron die bonding
• Conformal AR coatings

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MicroChem would like to thank Dow Electronic
Materials for providing these materials
and thank you for your time and attention.