IDEAL-IST Workshop

1
IDEAL-IST Workshop

• Christos P. Sotiriou,
• Institute of Computer Science,
• FORTH.
• sotiriou_at_ics.forth.gr

2
FORTH

• FORTH - Foundation for Research and Technology -
  Hellas.
• Established in 1983.
• Internationally recognised RD centre.
• 7 institutes, 280 Researchers, 735 Personnel
  (1999).
• 30,000,000E of annual budget.
• performs high-quality basic research.
• Development of innovative technologies.
• founder of many start-ups, FORTHnet is one of
  them.
• contributes to the development of
  ScienceTechnology parks.
• collaborates with the University of Crete and
  other Universities.

3
VLSI Group Activities

• Packet Switch Architectures (M. Katevenis)
• commodity switches.
• multi-gigabit switching fabrics with
  backpressure.
• Scalable Computing Infrastructures (A. Bilas)
• system area networks (SAN).
• single-system-image clusters.
• networks of autonomous sensors.
• Advanced Computing Systems (E. Markatos)
• Internet Systems and their Security.
• GRID computing and peer-to-peer systems.

4
VLSI Group Activities

• Network Processing (I. Papaefstathiou)
• High-throughput packet processing.
• On-the-fly compression and encryption.
• System Timing and Synchronisation (C. Sotiriou)
• Asynchronous circuit/system design
• low-power, low-EMI.
• Asynchronous design using commercial EDA tools.

5
System Timing Activities

• Coordinators of IST Project ASPIDA
  (IST-2002-37796).
• ASPIDA.
• (ASynchronous open-source Processor Ip of the
  Dlx Architecture).
• with Politecnico di Torino and Manchester
  University.
• Aim to develop an open-source, low-power,
  low-EMI, flexible-interface processor for
  embedded applications.
• fully-asynchronous CPU (DLX architecture).
• may be migrated to any fabrication technology.
• industrial quality testability (gt95).
• 2 processor bus interfaces
• WISHBONE synchronous Open on-chip bus
  (OpenCores).
• CHAIN novel asynchronous on-chip bus.

6
System Timing Activities

• members of the ACiD-WG (IST-1999-29119).
• Hosted the 3rd ACiD Workshop.
• Organising the 10th IEEE ASYNC conference.
• More about this at the end!
• Other informal research activities
• SOC interconnect design (asynchronous).
• EDA tool design (mainly synthesis).
• EDA flow design.
• Asynchronous FPGAs?

7
Asynchronous Technology?

• EMI Comparison (ARM9 vs. AMULET 3)

8
Asynchronous Technology?

• Power Density Comparison (Philips 80C51)

9
Asynchronous Technology?

• Deep SubMicron clocked designs
• clock distribution issues
• clock tree depth
• clock tree power consumption
• high ElectroMagnetic Interference (EMI)
• clock skew timing closure problems
• constant reduction of area reachable in 1 clock
  cycle
• continuous power consumption
• Example Designs
• DEC Alpha 21264 30-40 power to clock tree
• ARM9TDMI , 220MHz, 32 power to clock tree
• Pentium4 20 pipeline stages, 42M trans, 66Watts

10
ASPIDA RD

• RD activities in ASPIDA
• asynchronous circuit synthesis from standard
  HDLs.
• use of commercial EDA tools for asynchronous
  design
• Cadence, Synopsys based EDA flows.
• automated synthesis of asynchronous Control
  Circuits.
• relative timed (fast).
• speed independent (robust).
• automated synthesis of asynchronous Datapaths.
• automated scan chain insertion for ATPG
• asynchronous on-chip bus (CHAIN)
• low communication latency.
• no Signal Integrity problems.

11
ASPIDA Contribution
?DLX
12
ASPIDA CHAIN Interconnect
13
Collaboration/Ideas

• Collaboration in using/promoting asynchronous
  technology.
• Using/improving our technology on specific
  applications
• mobile and embedded systems.
• low-power, low-EMI systems.
• high performance? scalable asynchronous VLSI
  systems?
• mixed synchronous/asynchronous systems,
  interfaces and circuits.
• Comparing with possible alternatives
• optical clock networks, optical interconnects.
• Develop EDA tools for asynchronous design.

14
ASYNC 2004

• The 10th IEEE International Symposium
• on
• Asynchronous Circuits and Systems
• HERSONISSOS, CRETE, GREECE, 19-23 April 2004.
• http//www.ics.forth.gr/async2004,
• http//www.async04.gr.