CPU Design use pipeline

1
CPU Design use pipeline

• Xiang Gao and Dongsheng Chen

2
Design choice

• Why pipeline
• Pipeline would be faster then other choices
• No state machine
• No time difference
• Drawbacks of the pipeline design
• Without of Hazard detection unit and forwarding
• Relative address limitation 3 bits (-7 to 7)
• Jump and link (jal) needs more nops

3
Instruction type
Type Format Format Format Format
R opcode(15-12) rs(11-8) rt(7-4) rd(3-0)
I opcode(15-12) rs(11-8) rt(7-4) Imm(3-0)
J opcode(15-12) address(11-0) address(11-0) address(11-0)

• R types Add, Sub, And, Or, Slt, nop
• I types lw, sw, beq, bne, Addi, Sll,
• J types j, jr, jal

4
Control Unit

• Input
• opcode(15-12)
• Output
• branch_ctr, jump,
• Alu-src, M-wr, M_red, Mem to reg, Alu_op,
  reg_dst, branch, Reg_wr, Jal_wr

Branch_ctr
Control
jump
Alu_src
M_wr
15-12
memtoreg
Alu_op
Reg_dst
branch
reg_wr
Jal_wr
5
Control signal
6
Datapath
7
Simulation results
8
Test program
9
Simulation result
10
Question ?