Digital Electronics

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Digital Electronics
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Chapter 3
Gate-Level Minimization
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Karnaugh Maps
Simplify F A'B'C A'BC' AB'CA'BC ABC
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K-Map
Simplify F A'B'C A'BC' AB'CA'BC ABC
F C A'B
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K-Map with dont care
Simplify F(w,x,y,z) S (1,3,7,11,15) d(w,x,y,z)
S (0,2,5)
F z (y w' )
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DeMorgans Picture!
Two Equivalent Representations
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How Bubbles Move !
F AB CD
Three equivalent representations of F AB CD
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NAND Implementation
F xy' x'y z
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Designing for Equivalence
Design a circuit to check if x y
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Hint Review XOR and XNOR
XNOR will be high if x y
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Odd and Even Functions
(a) Checks for odd number of 1s (b) Checks for
even number of 1s
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Parity Generator / Checker
Even Parity Generator Even Parity
Checker P 1 if x,y,z have odd number of 1s so
that the four bits, x, y, z, and P have an even
number of 1s C 1 if there is error, that is if
the four bits received have an odd number of 1s
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VHDL
Verilog Hardware Description Language
// A simple example module my_example
(A,B,C,x,y) input A,B,C output x,y wire e and
g1 (e,A,B) not g2 (y,C) or g3 (x,e,y) endmodule
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Comments on my_example
// indicates a comment line statements are
terminated with endmodule has no
semicolon keywords like module, input etc. must
be in lowercase gate declarations must have the
output first then the inputs separated by commas
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Circuit Diagram of my_example
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Thats All Folks!